PhD thesis defence Johan Wernehag

Published: 2008-11-18

Date: 2008-12-12, at 10:15
Place: Lecture Hall E:1406, E-building, John Ericssons väg 4, Lund University, Faculty of Engineering, LTH
Opponent: Associate Professor Eric Klumperink. University of Twente, Department of Electrical Engineering
J. Wernehag:
Microwave CMOS Beamforming Transmitters
Department of Electrical and Information Technology, Series of licentiate and doctoral theses,Vol. 12,ISSN ISSN 1654-790X, Tryckeriet i E-huset, Lund., 2008.
Abstract: The increase of the consumer electronics market the last couple of decades has been one of the main drivers of IC process technology development. The majority of the ICs are used in digital applications, and for these CMOS is the choice of technology. The urge to squeeze more transistors on to a given area has led to shrinking feature sizes. It has resulted in higher transition frequencies and reduced supply voltage. During the last decade the increasing transition frequency has enabled CMOS to be used in RF applications, as well. Unfortunately, the decreasing supply voltage that, until recently, has accompanied the reduced feature sizes makes it more difficult to build power amplifiers that can deliver the amount of power needed to transmit the radio signal over the desired distance. In the receiver, the reduced supply voltage has resulted in reduced signal swing, which compromises linearity and dynamic range. In this thesis new topologies for the power amplifier is investigated, and the approach to combine the power from multiple power amplifiers is taken. In this way, despite the low supply voltage, the transmitted power by the IC can still be high. The increased transition frequency of CMOS technology can be used to increase the operating frequency to tens of GHz. The possibility for small sized phased antenna arrays then reveals, giving high directivity of the antenna and the potential for electrical beam steering. This both reduces interference to nearby receivers through spatial selectivity, and increases the equivalent isotropic radiated power. Power amplifiers with digital 360? phase control and antenna arrays have been investigated. In recent years applications at high operating frequencies have attained much focus from both academia and industry, such as automotive radar at 77 GHz andWLAN at 60 GHz. Even though the shrinking feature sizes of CMOS transistors have resulted in transit frequencies above 150 GHz, the high frequency required by many applications is still a great challenge for the CMOS designer. Therefore, in Paper IV and Paper VI different approaches to keep the on chip frequency lower than the RF carrier frequency as long as possible have been taken. In Paper IV two different frequency doubling 60 GHz power amplifier topologies are presented, and in Paper VI a subharmonic mixer with 30 GHz radio frequency and 15 GHz differential local oscillator is presented. Many transceiver architectures rely on quadrature signals driving the down- or upconversion mixers. The power amplifiers in Paper I and II need quadrature signals to implement the digital phase control. Therefore, in Paper V a three-stage active polyphase filter with quadrature output signals, high operation frequency, and wide bandwidth is analyzed. Analytical equations for both voltage gain and phase transfer function of a loaded stage are derived. The filter shows robustness against process parameter spread and achieves high quadrature signal quality from 6 GHz to 14 GHz.

PhD thesis defence Kristian Solem

Published: 2008-11-05

Date: 2008-11-28, at 10:15
Place: Lecture hall E:1406, E-building, John Ericssons väg 4, Lund University Faculty of Engineering
Opponent: Principal Research Scientist Gari Clifford. Laboratory for Computational Physiology at the Harvard-MIT Division of Health Sciences
K. Solem:
Signal Modeling and Detection in Nephrologic and Cardiac Applications
ISSN 1654-790X, No. 8, 2008.
Abstract: This doctoral thesis is comprised of five parts in the field of biomedical signal processing with focus on methods for use in hemodialysis as well as in cardiac applications. The problem of predicting hypotension is the main concern in the parts were data from patients undergoing hemodialysis are used. In Part I, a newly developed method for heart rate variability (HRV) analysis in the presence of ectopic beats, based on the recently published heart timing (HT) signal, is presented. The derived HRV method deals efficiently with the ectopic beats and is shown to have better performance than other existing methods as well as to be computationally very efficient. In Part II, the method from Part I is used to analyze the problem of hypotension on a database acquired from patients during hemodialysis. In addition, Part II also investigates other aspects from the ECG signal, namely, heart rate turbulence (HRT) and ectopic beat count (EBC). A method for early detection of hypotension, involving HRV and EBC analysis, is introduced, found to detect the cases of acute dialysis induced hypotension. It is suggested that the LF/HF ratio of the HRV spectrum and HRT are useful quantities for classifying patients as being either resistant or prone to hypotension. The integral pulse frequency modulation (IPFM) model is extended to account for the presence of ectopic beats and HRT in Part III. Based on this model, a new test statistic to detect and characterize HRT is presented. Three simulations were performed for the purpose of studying the influence of signal-to-noise ratio (SNR), QRS jitter, and ECG sampling rate on detector performance. The results show that the test statistic performs better in all simulations than do the commonly used parameters turbulence onset (TO) and turbulence slope (TS). In Part IV, the detector structure presented in Part III is further developed. A new detector, obtained from introducing a priori information to the detector structure, is presented. The a priori information consists of the average HRT shape and magnitude reflected in a weight vector. The results showed that the performance of the new detector outperformed that of the previously presented test statistic and TS on both simulations and real ECG data. Part V introduces a new method for prediction of intradialytic hypotension based on pulse oximetry. The method is based on a measure denoted relative magnitude of capillary pulse (RMCP), which reflects capillary vasoconstriction and cardiac output. The proposed method is able to predict all the cases in this study with acute intradialytic hypotension without producing any false alarms. In general, the prediction occurs early in time, allowing clinical staff to take actions to prevent the onset of hypotension or to alleviate symptoms.

PhD thesis defence Jianhua Cao

Published: 2008-11-25

Date: 2008-11-28, at 13:15
Place: Lecture hall E:1406, Department of Electrical and Information Technology, Ole Römers väg 3, Lund University Faculty of Engineering
Opponent: Prof. José Niño-Mora. Department of Statistics, Universidad Carlos III de Madrid
J. Cao:
Marginal Productivity Indices and Linear Programming Relaxations for Dynamic Resource Allocation in Queueing Systems
Series of Licentiate and Doctoral Thesis,ISSN 1654-790X No. 13, 2008.
Abstract: Many problems concerning resource management in modern communication systems can be simplified to queueing models under Markovian assumptions. The computation of the optimal policy is however often hindered by the curse of dimensionality especially for models that support multiple traffic or job classes. The research focus naturally turns to computationally efficient bounds and high performance heuristics. In this thesis, we apply the indexability theory to the study of admission control of a single server queue and to the buffer sharing problem for a multi-class queueing system. Our main contributions are the following: we derive the Marginal Productivity Index (MPI) and give a sufficient indexability condition for the admission control model by viewing the buffer as the resource; we construct hierarchical Linear Programming (LP) relaxations for the buffer sharing problem and propose an MPI based heuristic with its performance evaluated by discrete event simulation. In our study, the admission control model is used as the building block for the MPI heuristic deployed for the buffer sharing problem. Our condition for indexability only requires that the reward function is concavelike. We also give the explicit non-recursive expression for the MPI calculation. We compare with the previous result of the indexability condition and the MPI for the admission control model that penalizes the rejection action. The study of hierarchical LP relaxations for the buffer sharing problem is based on the exact but intractable LP formulation of the continuous-time Markov Decision Process (MDP). The number of hierarchy levels is equal to the number of job classes. The last one in the hierarchy is exact and corresponds to the exponentially sized LP formulation of the MDP. The first order relaxation is obtained by relaxing the constraint that no buffer overflow may occur in any sample path to the constraint that the average buffer utilization does not exceed the available capacity. Based on the Lagrangian decomposition of the first order relaxation, we propose a heuristic policy based on the concept of MPI. Each one of the decomposed subproblems corresponds to the admission control model we described above. The link to the decomposed sub-problems is the Lagrangian multiplier for the relaxed buffer size constraint in the first order relaxation. Our simulation study indicates the near optimal performance of the heuristic in the (randomly generated) instances investigated.

PhD course in optimization

Published: 2008-09-19

Beginning around 10 november Michal Pioro will start the PhD course "Integer programming with applications to engineering problems". Please contact Michal Pioro if you are interested.

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InfoCOM 2008 fredag 31/10

Published: 2008-10-25

Den 8:e upplagan av InfoCOM, elevkonferensen om data- och telekommunikation, hålls fredag 31/10 9-16 i E-husets hörsal B. Konferensen är öppen för besökande åhörare.

Konferensen är en del av examinatione i kursen ETS130 Kommunikationssystem som ges för C-programmets första årskurs.

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Disputation Suleyman Malki

Published: 2008-09-01

Date: 2008-10-17, kl: 10:15
Location: E:1406, E-building, Faculty of Engineering
Opponent: Dr. Piotr Dudek, University of Manchester

Abstract: Cellular Neural Networks are characterised by simplicity of operation. The network consists of a large number of simple nonlinear processing units; called cells; that are equally spread in the space, where each cell is fully connected to other cells in the immediate surrounding. A cell performs simple addition and multiplication operations and communicates with neighbouring cells through direct connections. Due to their intrinsic parallel computing power, CNNs have attracted the attention of a wide variety of scientists in, e.g., the fields of image and video processing, robotics and higher brain functions.

Simplicity of operation together with the local connectivity gives CNNs first-hand advantages for tiled VLSI implementations with very high speed and complexity. The first VLSI implementation has been based on analogue technology but was small and suffered from parasitic capacitances and resistances leading to undesired behaviour. Later implementations focus on larger network and high level of robustness. Mixed full-custom chips are most famous and widely considered as a roadmap for advanced realisations. The digital counter parts have focused on emulating the functionality of the CNN rather than providing real-time performance. Furthermore, they are totally dependent on a host PC to function properly. In spite of being less sensitive to parasitic noise and fabrication artefacts beside providing a quasi-infinite accuracy, fully digital implementations are, however, still not available. In other words, the exploitation of a stand-alone fully-digital approach is highly desired, which this thesis aims to tackle.

Macro enriched Field-Programmable Gate-Arrays (FPGAs) are used to realise such systems on silicon. At first glance a pipelined approach, based on circuit switching, seems promising. Two different approaches are investigated; Spatial and Temporal, of which the former is to prefer. The best digital implementation supports the handling of grey-level images at 180 to 240 Mpixels per second by exploiting the Xilinx Virtex-II macros to spatially unroll the local feedback. Later on, in order to overcome design limitations and thus enhance performance, the benefits of packet-based switching have been explored. Although circuit switching is still employed, the enhancement is achieved by adopting the concept of Network-on-Chip (NoC), where packets are transmitted in a predefined communication pattern. The choice is between Serialized and Switched broadcasting schemes. The digital implementation of the Switched broadcasting is performed using Xilinx Virtex-II Pro P30 and the advantages over the pipelined approach are discussed by means of clock rate, area utilisation and memory considerations. A serial communication approach shows, however, that network size can be increased further by a clear decrease in the size of communication interface. The thesis illustrates the power of the different implementations experimentally. It is shown how these implementations can be used to estimate velocity from images or to facilitates authentication by means of vein feature extractions. Furthermore, the issue of robustness is discussed from a different point of view. Here, the limited accuracy is compensated by gradual adjustment of the operative parameters, i.e. template coefficients. Finally, the thesis discusses main ingredients in system architecture to achieve the goal of a stand-alone fully-digital design.

Disputation Henrik Svensson

Published: 2008-08-28

Date: 2008-10-03, kl: 10:15
Location: E:1406, E-building, Faculty of Engineering
Opponent: Jari Nurmi, Tampere University of Technology

Abstract: Migrating computer systems from workstations to handheld devices, while maintaining sufficient performance within the budget for physical size and energy dissipation, have required application-specific circuits. Application-specific circuits are inflexible as any modification requires redesign and refabrication, which is both expensive and time consuming considering the complexity of recent embedded platforms. Therefore, reconfigurable architectures that can be dynamically reconfigured and reused over several platforms have been suggested and they have proven to provide high performance in a wide range of applications.

This thesis focuses on two important topics when designing reconfigurable embedded systems: coarse-grained reconfigurable architectures and system level architectural exploration. It is argued that embedded systems requiring programmable hardware acceleration of regular compute intensive kernels with wide-word arithmetic should utilize coarse-grained reconfigurable architectures, and that design of these complex systems should be performed with tools for efficient modeling, simulation, and architectural exploration in order to analyze and tune design parameters before a chip is fabricated. This thesis presents two different coarse-grained reconfigurable architectures and also a modeling and exploration environment to build and explore complete reconfigurable computing platforms.

The first reconfigurable architecture consists of a number of locally interconnected processing elements and memory banks. The processing elements are configured into customized datapaths and the memory banks are used to move data back and forth from the datapath at high data rates. The reconfigurable architecture was integrated as a coprocessor and used to accelerate the G.723.1 speech codec. It is shown that the number of used clock cycles are reduced with 83% compared to processor only execution. The second reconfigurable architecture is built as an array of small instruction set processors and memory blocks, which are interconnected with local dedicated wires and a global hierarchical routing network. To address efficient architectural exploration, a SystemC Environment with Interactive Control (SCENIC) is presented. The reconfigurable architecture is described as a scalable and parameterizable SystemC transaction level model, and to evaluate a complete system, models of instruction set processors, busses, and memories are developed.

Disputation Marcus Nyström

Published: 2008-08-28

Date: 2008-09-26, kl: 13:15
Location: E:C, E-building, Faculty of Engineering
Opponent: PD Dr. -Ing. Erhardt Barth, Lubecks Universitet

Abstract: With the continued growth of digital services offering storage and communication of pictorial information, the need to efficiently represent this information has become increasingly important, both from an information theoretic and a perceptual point of view.

There has been a recent interest to design systems for efficient representation and compression of image and video data that take the features of the human visual system into account. One part of this thesis investigates whether knowledge about viewers' gaze positions as measured by an eye-tracker can be used to improve compression efficiency of digital video; regions not directly looked at by a number of previewers are lowpass filtered. This type of video manipulation is called off-line foveation. The amount of compression due to off-line foveation is assessed along with how it affects new viewers' gazing behavior as well as subjective quality. We found additional bitrate savings up to 50% (average 20%) due to off-line foveation prior to compression, without decreasing the subjective quality.

In off-line foveation, it would be of great benefit to algorithmically predict where viewers look without having to perform eye-tracking measurements. In the first part of this thesis, new experimental paradigms combined with eye-tracking are used to understand the mechanisms behind gaze control during scene perception, thus investigating the prerequisites for such algorithms. Eye-movements are recorded from observers viewing contrast manipulated images depicting natural scenes under a neutral task. We report that image semantics, rather than the physical image content itself, largely dictates where people choose to look. Together with recent work on gaze prediction in video, the results in this thesis give only moderate support for successful applicability of algorithmic gaze prediction for off-line foveated video compression.

Seminar by Craig F. Bohren

Published: 2008-09-17

from Pennsylvania State, USA
Date: Wednesday, Sep. 24, 13.15
Location: E:2311
Title: Who Nose? The Chemistry, Physiology, Psychology, Physics, Meteorology, and Fluid Mechanics of Canine Olfactory Tracking
Abstract: Olfaction cuts across many branches of science, from physics to physiology to psychology. Scientific interest in olfaction is increasing, both for its intrinsic interest and for practical reasons. Dogs are used for tracking, for detecting explosives, fire accelerants, buried mines, narcotics, and termites. Understanding how dogs and other animals, even insects, detect scent and distinguish one scent from another may enable better instruments to be designed. And olfaction is at the frontier of basic research on sensations. The scale of the olfactory world ranges from subatomic to organismic, even to the supra-organismic dog and handler team.

Disputation Christian Sohl

Published: 2008-08-27

Date: 2008-09-23, kl: 10:15
Location: E:1406, E-building, Faculty of Engineering
Opponent: Prof. Craig F Bohren, Pennsylvania State University, USA.

Abstract: This dissertation deals with physical bounds on scattering and absorption of acoustic and electromagnetic waves. A general dispersion relation or sum rule for the extinction cross section of such waves is derived from the holomorphic properties of the scattering amplitude in the forward direction. The derivation is based on the forward scattering theorem via certain Herglotz functions and their asymptotic expansions in the low-frequency and high-frequency regimes. The result states that, for a given interacting target, there is only a limited amount of scattering and absorption available in the entire frequency range. The forward dispersion relation is shown to be valuable for a broad range of frequency domain problems involving acoustic and electromagnetic interaction with matter on a macroscopic scale. In the modeling of a metamaterial, i.e., an engineered composite material that gains its properties by its structure rather than its composition, it is demonstrated that for a narrow frequency band, such a material may possess extraordinary characteristics, but that tradeoffs are necessary to increase its usefulness over a larger bandwidth.

The dispersion relation for electromagnetic waves is also applied to a large class of causal and reciprocal antennas to establish a priori estimates on the input impedance, partial realized gain, and bandwidth of electrically small and wideband antennas. The results are compared to the classical antenna bounds based on eigenfunction expansions, and it is demonstrated that the estimates presented in this dissertation offer sharper inequalities, and, more importantly, a new understanding of antenna dynamics in terms of low-frequency considerations.

The dissertation consists of 11 scientific papers of which several have been published in peer-reviewed international journals. Both experimental results and numerical illustrations are included. The General Introduction addresses closely related subjects in theoretical physics and classical dispersion theory, e.g., the origin of the Kramers-Kronig relations, the mathematical foundations of Herglotz functions, the extinction paradox for scattering of waves and particles, and non-forward dispersion relations with application to the prediction of bistatic radar cross sections.

Fulltext: http://luur.lub.lu.se/luur?func=downloadFile&fileOId=1221236

HSWC Distinguished Lecture (open to all): Location, Location, Location

Published: 2008-08-21

Moe Win, Laboratory for Information and Decision Systems (LIDS),
Massachusetts Institute of Technology.
http://wgroup.lids.mit.edu/

Date: Friday, 29 Aug 2008.
Time: 10.15-11.30am.
Venue: Lecture Hall E:1406 (northern end, ground floor), E-Building, LTH, Lund University.


Abstract.
The availability of positional information is of great importance in many commercial, public safety, and military applications, including social networks, vehicle routing, intruder detection, search-and-rescue operations, and blue force tracking. With the integration of GPS into cell phones, in conjunction with WiFi localization, we are entering a new era of ubiquitous location-awareness. The coming years will see the emergence of high-definition location-awareness (HDLA) with sub-meter accuracy, with minimal infrastructure requirements, even in the harshest environments, and the most dire of circumstances. HDLA relies on a combination of ultra-wide bandwidth (UWB)transmission and cooperative peer-to-peer (P2P) algorithms. This talk will present a cooperative localization in UWB networks from three points of view: fundamental performance bounds, cooperative algorithms, and experimentation.

19-6-2008: Master Thesis Presentation

Published: 2008-06-18

On Thursday June 19 at 9:15 Erika Gamero will present her master project “Connecting Real Accessories to a Simulated Environment", done in cooperation with SonyEricsson in E:2311, Orangeriet.

Abstract
========
The objective of this master thesis was to study the Sony Ericsson’s A1 System Connector and to create an interface capable of connecting real accessories to the Sony Ericsson’s phone simulator (SESAM), this was done with an ATMEL AT91SAM7S256 lab board which was programmed and adapted to the simulator.

The Resistive Identification (RID) process was studied and implemented as well as the data communication through the Accessory Control Bus (ACB) and the External Data Bus (EDB). During the development process electronic devices such as Analog-to-Digital Converters (ADCs), Direct Memory Access (DMA), UARTs, buffers and inverters were studied.

The SESAM simulator was expanded with the implementation of the accessory identification and the communication through the ACB bus, the EDB communication was developed on its first level.

The specifications on how this project was done can be found on this Master Thesis report.

13-6-2008: Master Thesis Presentation

Published: 2008-06-13

Today (Friday) at 10:15 Christopher Sturk and Erik Adlers will present in E:3139 the results of their ExJobb project “Energy Efficient Digital Signal Processing on Multi-Core Architectures”. The project has been done at Ericsson Research under supervision of Leif Wilhelmsson and Jim Svensson. Abstract. Wireless communication platform developers are facing an increasing amount of communication standards to support. WiMax and 3G Long Term Evolution(LTE) are for example two competing standards in the high data rate field. Due to this, new flexible multi-standard platforms have to be developed to handle the presence of multiple communication standards. The trend is to move from ASIC implementations to a hardware architecture able to handle multi-standard co-existence. In out thesis we will evaluate the possibility to implement channel estimation algorithms on a multi-core architecture. The main purpose is to study scalability of different algorithms, and evaluate them with respect to power consumption and performance.

12-6-2008: Master Thesis Presentation

Published: 2008-06-09

David Herrero's Master thesis presentation entitled "Application-focused traffic measurements in IP access networks" will be held 12/6 at 10.15 in E:3139.

The project is part of our CELTIC project "Traffic measurements and models in multi-service networks (TRAMMS)".

The purpose of the project has been to analyze Internet user behavior, in particular which applications people are using, and how much data they are generating. P2P file sharing, streaming and online gaming behavior and traffic patterns have been studied in more detail.

2008-06-11: LICENTIATSEMINARIUM

Published: 2008-05-20

"Spatial Characterization of Atrial Fibrillation Using Body Surface and Intra-Atrial Signals"

Civ. ing. Ulrike Richter

Seminariet kommer att hållas onsdagen den 11 juni 2008, kl. 13.15 i E:2311 (Orangeriet), inst. för elektro- och informationsteknik, E-huset, LTH

Doc. Urban Wiklund Umeå universitet kommer att agera som granskare
Ämne: Signalbehandling (avh. omfattning 40p)
Rapporten finns tillgänglig vid institutionen (hos sekreterare)
Handledare: Martin Stridh och Leif Sörnmo

2008-06-10: Exjobbspresentation

Published: 2008-06-09

Maria Leyre Cendrero Mateo och Maria Jose Castellanos Parra redovisar sitt examensarbete "Phase rectified signal averaging for circadian analysis of atrial fibrillation" tisdagen den 10/6, kl. 15.15-16.00 i Orangeriet på inst. för elektro- och informationsteknik (vån 2).

9-6-2008: Master Thesis Presentation

Published: 2008-06-02

On Monday June 9th Amit Singh is presenting his Master’s thesis at 10.15 in E:2311. The thesis deals with channel properties for sensor networks, both indoor and outdoor. Together with Shurjeel Wyne, Amit has made one of the first investigations of the true channel conditions for such applications. The presentation will be around 20 min and you are all welcome to attend.

Dissertation 05-06-2008

Published: 2008-03-11

Martin Andersson defends his doctoral thesis "CMOS A/D Converters for Communications" (preliminar title) at a public dissertation on Thursday 5th of June 2008 at 13.15i E:1406. Faculty opponent is Prof. Franco Maloberti, University of Pavia, Italy.

Abstract:
=========
A high-performance and flexible analog-to-digital converter (ADC), that can be integrated in deep-submicron CMOS technology, is a key building block for reduced size, cost and power consumption of digital communication systems. This dissertation concerns the investigation of particular problems associated with the design of such ADCs. The problem of increased clock jitter sensitivity of low-pass (LP), 1-bit, continuous-time (CT) Delta-Sigma modulators with return-to-zero (RZ) feedback is studied. A high-level behavioral model is developed that can be used to simulate the dominant clock phase noise effects, with arbitrary clock phase noise and input signals, quickly and accurately. The accuracy of the presented model is verified by measurements on a second order LP CT Delta-Sigma modulator circuit with switched current (SI) RZ feedback digital-to-analog converter (DAC). As part of the verification a simulation and measurement technique is developed that enables studies of the clock phase noise sensitivity for different frequency offsets separately. It is found by simulations that the wide-band clock phase noise, modulating the amount of charge delivered, per clock period, by the traditional SI (RZ) feedback DAC, is the dominating effect in many practical situations. To reduce the sensitivity to wide-band clock phase noise, a switched-capacitor switched-resistor (SCSR) feedback DAC concept is proposed, which makes the amount of charge per clock period less dependent on the exact timing of the clock edges. The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrator(s). A functional level analysis of the trade-offs between the reduction of the pulse-width jitter sensitivity, the DAC output peak current and the SC discharge time constant is carried out. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5-mW, 312-MHz, second order, LP, 1-bit, CT Delta-Sigma modulator with SCSR feedback has been implemented in a 1.2-V 90-nm RF-CMOS process. A signal-to-noise ratio (SNR) of 66.4dB and a signal-to-noise-and-distortion-ratio (SNDR) of 62.4dB is measured in a 1.92MHz bandwidth. The measurements show that the sensitivity to wide-band clock phase noise is reduced by 30dB compared to a traditional SI (RZ) DAC. Additionally, the problems with offset and gain mismatch between the ADC units in a randomly time-interleaved successive-approximation (SA) ADC system is studied by measurements of a 12-bit, 30-MSPS, randomly time-interleaved SA-ADC circuit. The effectiveness of previously presented error estimation and equalization algorithms is verified using the measured data, through an SNDR improvement of more than 10dB after error equalization. Moreover, a sampling rate and resolution reconfigurable pipeline/cyclic ADC is proposed. Circuit techniques developed to enable the reconfiguration is presented. A 10-bit 80-MSPS pipeline/cyclic ADC, with 8 configurations, has been implemented in a 0.18-um CMOS process. The ADC performance is verified by measurements.

4-6-2008: Master Thesis Presentation

Published: 2008-06-04

On Wednesday, June 4th, Luyu Wang will present his Master’s thesis, "Design and Simulation of Ultra-Wide-Band Low Noise Amplifiers in 90nm CMOS", at 10.15 in E:2311.

Abstract:
=========
In this thesis, two double stages LNA are designed based on the UMC 90 nm process for UWB application. Both of them use negative feedbacks at input and output stage to stabilize the gain, and also set the terminal impedance over the band of interest. Thereby the 20.25dB and 21dB with 0.5dB and 0.75dB variation is achieved respectively. Noise figure is 2.69dB and 1.3dB with 0.04dB, 0.05dB variation over the entire UWB band respectively. A good input and output matching is reported as S11 below -12.5dB , -10 dB and S22 is below -10dB, -8 dB over the desired band respectively. Bias current-reuse provide lower power consumption, both of the two LNA have 8.9mA bias current at 1.2V supply.

03-06-2008: Dissertation

Published: 2008-04-09

Thomas Lenart defends his thesis "Design of Reconfigurable Hardware Architectures for Real-time Applications - Modeling and Implementation Aspects" at a public dissertation 03-06-2008 at 09.15 in E:1406. Fakulty opponent is Prof. Dr.-Ing. Jürgen Teich, University of Erlangen-Nuremberg

Abstract
========
This thesis discusses modeling and implementation of reconfigurable hardware architectures for real-time applications. The target application in this work is digital holographic imaging, where visible images are to be reconstructed based on holographic recordings. The reconstruction process is computationally demanding and requires hardware acceleration to achieve real-time performance. Thus, this work presents two design approaches, with different levels of reconfigurability, to accelerate the image reconstruction process and related computationally demanding applications.

The first approach is based on application-specific hardware accelerators, which are usually required in systems with high constraints on processing performance, physical size, or power consumption, and are tailored for a certain application to achieve high performance. Hence, an acceleration platform is proposed and designed to enable real-time image reconstruction in digital holographic imaging, constituting a set of hardware accelerators that are connected in a flexible and reconfigurable pipeline. Hardware accelerators are optimized for high computational performance and low memory requirements. The application-specific design has been integrated into an embedded system consisting of a microprocessor, a high-performance memory controller, a digital image sensor, and a video output device. The system has been prototyped using an FPGA platform and synthesized for a 0.13 μm standard cell library, achieving a reconstruction rate of 30 frames per second running at 400 MHz.

The second approach is based on a dynamically reconfigurable architecture to accelerate arbitrary applications, which presents a trade-off between versatileness and hardware cost. The proposed reconfigurable architecture is constructed from processing and memory cells, which communicate using a combination of local interconnects and a global network. High-performance local interconnects generate a high communication bandwidth between neighboring cells, while the global network provides flexibility and access to external memory. The processing and memory cells are run-time reconfigurable to enable flexible application mapping. Proposed reconfigurable architectures are modeled and evaluated using Scenic, which is a system-level exploration environment developed in this work. A design with 16 cells is implemented and synthesized for a 0.13 μm standard cell library, resulting in low area overhead when compared with application-specific solutions. It is shown that the proposed reconfigurable architecture achieves high computation performance compared to traditional DSP processors.

3-6-2008: A Link Layer Simulator for MIMO etc.

Published: 2008-05-03

On Tuesday June 3 at 15.15 in Orangeriet, Prof. Svante Signell, KTH, will present a Link Layer Simulator developed at KTH.

Title: LiLaS: A Link Layer Simulator in Matlab/Octave

Abstract:
This paper describes a generic link layer simulation environment for multiple antenna systems in MATLAB and OCTAVE, for both Windows and Unix/Linux operating systems: LiLaS. The simulator is functionally divided into modules, sub-modules and models with a common interface for the convenience of modification and reconfiguration. Currently, it accommodates a variety of transmission schemes, including single-carrier multiple-input multiple-output (MIMO), Orthogonal Frequency-Division Multiplexing (OFDM), multi-carrier MIMO, OFDM/Offset QAM, Wideband Code Division Multiple Access (WCDMA), filtered multitone (FMT) and RFID which have extensive applications in modern communication technologies, e.g., WLAN 802.11 a/b/g/n, WiMAX, UWB, 3G, B3G, LTE, xDSL, DVB, etc.

2-6-2008: Seminar on "Time Reversal for Ultra-wideband Wireless Communications".

Published: 2008-05-28

Our guest from Tennessee Tech University, Dr. Robert Qiu, will give a seminar on "Time Reversal for Ultra-wideband Wireless Communications". The seminar will be at 15.15 in E:2311 (Orangeriet), on Monday June 2. You are all welcome to attend! Telmo Santos telmo.santos@eit.lth.se Biography of the presenter: http://iweb.tntech.edu/rqiu/Robert%20Qiu.htm Presentation abstract: Time Reversal for Ultra-wideband Wireless Communications Ultra-wideband (UWB) impulse radio is a revolutionary, power-limited technology for its unprecedented system bandwidth. The low emission and impulsive nature of UWB radio leads to enhanced security in communications. Good through-wall penetration capability makes UWB systems suitable for hostile, indoor environments. UWB impulse radio can be potentially implemented with extremely low-cost (sub-one dollar) and low-power (battery driven) consumption components. Time-hopping can be used to provide its robustness to interference. UWB systems are immune to fading (more reliable to use) as compared with narrowband systems, since the high resolution of short pulses (sub-nanosecond) leads to almost static channels with a large number of resolvable paths that are challenges to others but can be exploited by the proposed new techniques; this feature is relevant to “disadvantaged platforms and sensors” (e.g., small-deck combatants and dispersed ground units) in RF challenged environments of dense multipath in the presence of buildings and obstacles. Therefore, UWB impulse radio represents a secure solution to robust and extremely energy-efficient sensor networking (REEESN) for both unattended ground sensors and floating surveillance sensors in urban and littoral environments. Within buildings the-state-of-the-art is the capability to support a bit-rate of Mbps over distances of tens of meters. The most pressing challenge is, however, how to reduce the transceiver complexity of coherent reception. The proposed system paradigm uses time-reversal with non-coherent detection as an alternative to coherent reception. It exploits the hostile, rich-multipath channel as part of the receiver chain. This new method also combines time-reversal with MIMO, the most promising approach to use spectrum and transmission power. As a result, time-reversal trades the huge bandwidth of UWB radio and the high power efficiency of MIMO for the non-coherent detection of extremely low cost. This proposed new system paradigm is to take advantage of the impulse nature of UWB signals. The new dimension of impulsive time-reversal adds more degrees of freedom in exploiting the spatiotemporal dimensions. The proposed system framework can potentially be a solution to the pressing problem of range extension for UWB sensors. The proposed research will potentially lead to revolutionary breakthroughs in many branches such as the wireless industry, UWB radar and sensors, underwater acoustics, remote sensing, and image-guided therapy and surgery. The design of the test-bed will be covered; the movie will demonstrate the test-bed experimentally. We will also cover some extensions of the test-bed to some new directions such as cognitive radios using compressed sensing. The project is funded by ARL, ARO, NSF and ONR.

29-5-2008: NRC Seminar

Published: 2008-05-28

Its time for the last seminar this spring from the Neuronano Research Centre.

THURSDAY MAY 29th, 15:30-16:30 Segerfalkssalen, BMC A10. Mingle 15:00-15:30.

Professor Patrick Tresco, Department of Bioengineering, University of Utah "The Challenge of Integrating Materials into the Nervous System for Long-term Applications" http://www.bioen.utah.edu/faculty/PAT/

This NBC seminar is hosted by the Neuronano Research Center - NRC http://www.med.lu.se/nrc/events

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30-05-2008: Dissertation

Published: 2008-04-14

Lars Aspemyr will defend his PhD thesis "Microwave CMOS LNA:s and VCO:s - using passives on chip, above chip, and beside chip" (preliminary title) at a public dissertation on Friday May 30, 2008 at 13.15 in E:1406. The faculty opponent is Prof. Jussi Ryynänen, Helsinki University of Technology, Finland.

ABSTRACT
========
The performance of LNAs and VCOs is of large importance to the complete wireless communications system. To achieve sufficient performance in microwave applications, LNAs and VCOs have therefore up to now mostly been manufactured in advanced and expensive semiconductor technologies. In this thesis it is shown, however, that by using a standard CMOS technology, combined with different packaging and post processing techniques, it is now possible to achieve both excellent microwave performance and low cost.

The rapid technology advancements have lately made CMOS an attractive alternative for RF/microwave applications. The high fT and fmax, the low minimum noise figure, and the excellent integration capabilities are all in favor of modern CMOS technology. The improved high frequency performance of MOS transistors is primarily a result of gate length scaling, but also strongly depends on process and layout optimization. To design state-of-the-art RF/microwave circuits, a thorough understanding of device physics and transistor models is thus necessary. These issues are therefore investigated, particularly focusing on small-dimension effects and high frequency modeling. While device speed and minimum noise factor improve with scaling, the 1/f noise and linearity trends are less obvious. The expected impact of technology scaling on the performance of LNAs and VCOs is therefore also discussed.

If noise performance is the main focus of the design, the quality-factor (Q) of the passive components can be as important as the performance of the transistors. If inductors are realized using the standard interconnect layers of the CMOS process, the strong coupling to the conductive substrate results in a reduced Q-factor. The Q-factor can therefore be improved by placing the inductors higher above the conducting substrate, using post-processing with thick BCB and top metal, or by moving them off-chip and integrating them on a carrier. Both principles are evaluated in this thesis. For VCOs oscillating at frequencies well above 10 GHz, the semiconductor varactor, rather than the inductor, limits the phase noise performance. Varactors based on ferroelectric films have very high Q-factors at these frequencies, but unfortunately the technology is not yet compatible with the IC fabrication process. In this thesis, designs based on CMOS dies flip-chip mounted on carriers with ferroelectric varactors have therefore been evaluated.

The seven papers included in this work show the potential of CMOS for LNA and VCO design at microwave frequencies. They also investigate the potential of alternative packaging methods, as the passive components are placed either on-chip, above chip, or off-chip. Papers III, IV, V, and VII demonstrate LNAs operating from 5 GHz to 20 GHz, and in Papers I, II, and VI, VCOs operating up to 30 GHz are presented. Several of the Designs show state-of-the-art performance.

30-5-2008: Master Thesis Presentation

Published: 2008-05-30

Today Adam Fejne will present his master project “Evaluation of Attack Methods on Light-weight Symmetric Ciphers” at 11.15 in E:3139.

-=Abstract=-
Algebraic cryptanalysis deals with describing a cipher as a set of equations over a finite field, often GF(2). Solving these equations reveals the key (or some other unknown parameter) used in the ciphering process. Solving multivariate polynomial equations over finite fields is in general an NP-hard problem, but, since the equations representing a cipher often are symmetric and sparse, one has reason to believe that faster algorithms exist for these particular cases.

Lately there has been some new development in the field and some new algorithms have been proposed. Among them is the recently discovered Agreeing-Gluing algorithm by Semaev. Another approach is to transform the system of equations into a Boolean Satisfiability problem and solve it using a SAT-solver (i.e. MiniSAT). One suspects that these methods work especially well on light-weight ciphers.

The objective of this thesis is to implement some of these methods (SAT-solvers/agreeing-gluing) and test their efficiency on KeeLoq. It aims to investigate the usefulness of the different approaches and compare them to each other.

28-5-2008: Master Thesis Presentation

Published: 2008-05-28

On Wednesday May 28 at 14:15 Sagar Jagtap presents his master project “Constraints quality checks for timing closure of a complex digital ASIC", done in cooperation with EMP in E:3139.

Abstract
========
For today’s rapidly scaled down technology precise timing analysis is a crucial step in IC design. Quality of constraints dictates the quality and the speed of implementation. Complex design projects go through a few iterations due to constraints issues. Therefore the burden of overall constraints effectiveness is on the design engineers across the development process.

Therefore we should not be surprised, that, design community are recognizing the need to rethink and redefine constraints that improves the quality of the IC design task. This thesis work exposes basic concepts of timing analysis and quality issues of design constraints. Semiconductor business operates in the world of compressed time and hypercompetition. To compete effectively in this business automation of design steps using different EDA tools improves time-to-market metric. This thesis work investigates needful automated tool flows and techniques depending on the context.

9-5-2008: Seminar on Optimization Tools

Published: 2008-04-29

Invitation to a seminar on optimization tools on 9th of May at 13.15 in Orangeriet. Speaker is Håkan Strandberg, ESTECO Nordic AB.

All interested in simulation and optimization are welcome!

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9-5-2008: Master Thesis Presentation

Published: 2008-05-06

Friday 9-May at 13.15 Anna Maria Garcia Hervàs and Alfredo C. López Salcedo presents their Master Thesis "Automation of Java Performance Tests" in E:3139.

Abstract:
=========
This Master Thesis is focused on the development of a tool to automate the performance testing process on Sony Ericsson mobile phones. The main goal has been to automate the process as much as possible, thus reducing the time testers spend on repetitive tasks. The application has been developed in Java SE with connection to a remote Microsoft SQL database.

7-5-2008: Master Thesis Presentation

Published: 2008-05-07

On Wednesday May 7 at 14:15 Huan Ren presents her master project “Implementation of a Binary Erosion and Dilation Hardware Accelerator" in E:3139.

Abstract
========
Binary morphological operations are an important means for real-time image processing applications. Erosion and dilation are the two fundamental operations, since all morphological operations can be broken down into these two basic ones. The goal of this thesis is to implement a single erosion and a single dilation unit in FPGAs. The implementation of this unit is intended as a hardware accelerator. The accelerator has been implemented and successfully verified on a Xilinx Virtex-II pro XC2VP30 platform. The accelerator can handle several different resolution and the maximum frame rate will vary accordingly, e.g. at 640x480 it can process 490 fps. By placing multiple units in series, other extended morphological operations can be performed such as opening and closing.

2008-05-02: Exjobbspresentation

Published: 2008-05-02

Välkommen till exjobredovisning idag kl 10.15 i 3139 av Johannes Höier Sörensen examensarbete "Application Management on a Secure Element" utfört på Ericsson Research i Kista.

Abstract:
=========
The mobile phone is becoming more and more our everyday tool and new applications that can be added, to increase the usability, are constantly being investigated. The purpose of this thesis is to analyze how a system to manage these applications can be implemented, develop a proof-of-concept and to theorize on how to expand this proof-of-concept to a commercial system. To explain the analysis, four models are described, which range from showing a simple system to showing a more advanced system. Concepts such as using a Broker and a CP are covered. These models lead to two use cases that illustrate different ways for how a system actually can be implemented. Furthermore, a proof-of-concept is presented along with some issues that were solved. Additionally, the thesis describes the process of developing the proof-of-concept. Finally, an idea of what needs to be done to further build upon this system is also offered.

2008-04-24: Master Thesis presentation

Published: 2008-04-19

On Thursday 24 April at 15:15 Markus Widing presents his master project Induction Heating of Composite Materials, in E2311. The project is done in cooperation with Tetra Pak.

Abstract
========
In this thesis the Tetra Pak Induction Heater (TPIH) is studied. An analytical solution of the electromagnetic part of the problem is developed and the thermal part of the problem is solved with the parabolic command in Matlab. An iterative solver that solves both the electromagnetic and the thermal parts for consecutive time steps is implemented in Matlab. The thermal and electric properties of the material are updated for each time step. With this program the temperature distribution from a pulse of any given power and length can be calculated. A method for measuring the temperature is also developed and used to verify the results of the calculations.

The calculations agree very well with the measurements and the accuracy of the mathematical model is thereby verifed. The program developed in this thesis could be very useful when predicting temperatures in different materials and different pulses in the TPIH.

11-04-2008 Dissertation

Published: 2008-04-08

On Friday, April 11 at 10.15 in E:1406, Hugo Hedberg will defend his Thesis for the Doctoral degree: "Image Processing Architectures for Binary Morphology and Labeling"

Faculty Opponent: Associate Professor Christophe De Vleeschouwer, Université Catholique de Louvain, Belgium

Abstract
========
Conventional surveillance systems are omnipresent and most are still based on analog techniques. Migrating to the digital domain grants access to the world of digital image processing enabling automation of such systems, which means extracting information from the image stream without human interaction. The resolution, frame rates, and functionality in these systems are continuously increasing alongside the number of video streams to be processed. The sum of all these parameters imposes high data rates and memory bandwidths which are impossible to handle in pure software solutions. Therefore, accelerating key operations and complex repetitive calculations in dedicated hardware architectures is crucial to sustain real-time performance in future advanced high resolution and frame rate systems.

To achieve this goal, this thesis presents four architectures of hardware accelerators to be used in real-time embedded image processing systems, implemented as an FPGA or ASIC. Two morphological architectures performing binary erosion or dilation, with low complexity and low memory requirement, have been developed. One supports static, and the other locally adaptive flat rectangular structuring elements of arbitrary size. Furthermore, a high-throughput architecture calculating the distance transform has also been developed. This architecture supports either the city-block or chessboard distance metric and is based on adding the result of parallel erosions. The fourth architecture performs connected component labeling based on contour tracing and supports feature extraction. A modified version of the morphological architecture supporting static structuring elements, as well as the labeling architecture, has been successfully integrated into a prototype of an automated digital surveillance system for which implementation aspects are presented. The system has been implemented and is running on an FPGA based development board using a CMOS sensor for image acquisition. The prototype currently has segmentation, filtering, and labeling accelerated in hardware, and additional image processing performed in software running on an embedded processor.

2008-04-08 Exjobbspresentation i nanoteknik

Published: 2008-03-28

På tisdag den 8 april presenterar Christian Larsen sitt exjobb 'Modelling of WIGFET for implementation in circuit designs'

Plats: E:2311
Tid: kl 15.00

Abstract:
=========
The wrapped insulator gate field effect transistor fabricated bottom up from compound semiconductor nanowires provide better control of the channel potential than ordinary field effect transistor technologies, which ensures higher transconductance and reduces short channel effects as the gate lengths are scaled. The possibility of integration onto silicon wafers makes the wrapped insulator gate field effect transistor an interesting alternative to silicon and silicon/germanium transistors due to the higher mobility of the compound semiconductors and the possibility of abrupt heterostructures in the wire. This work presents a scalable model of a high frequency structure of the vertical wrapped insulator gate field effect transistor, based fully on analytical expressions to reduce simulation times. The model was developed for implementation in Verilog-A and simulations using CADENCE. Simulation indicates a cut-off frequency 251.0 GHz and a maximum oscillation frequency of 237.5 GHz for an 81 wire transistor. These values are simulated including the parasitic components and the model allows for closer investigation of these parasitic elements to determine the transistor geometry optimized for maximum performance. The results presented in the report confirm that the wrapped insulator gate field effect transistor could be a strong candidate to replace the standard planar technology in high-speed and low power applications.

2008-04-08: Master Thesis Presentation

Published: 2008-04-02

Welcome to the Master of Science Thesis presentation “Low Leakage Arithmetic” by Qihang Shi and Umer Hasnain at 14.00 on Tuesday, April 8 in E:2311 (Orangeriet)

Abstract
========
With the increase in complexity of the digital circuits, the power consumption is becoming a major obstacle in upcoming technologies. The dynamic power has been the major concern from the power consumption perspective in digital CMOS circuits. However, in today’s technologies it can be noticed that the static power consumption is an important factor for the total power consumption.

Introduction of new technologies result in smaller and faster transistors involving importance of static power dissipation. Alternatives are bit- and digit-serial arithmetic, which shows good properties to reduce the static power consumption. Many different techniques are used to reduce power consumption and leakage at the circuit level.

The thesis work is based on the use of other arithmetic than the traditional bit-parallel. Performance comparison of the bit-parallel and bit-serial designs shows the reduced static power dissipation in the bit-serial design through using fewer components at higher frequencies. Less transistor count in bit-serial design has made possible less leakage power dissipation as low as 1/6 of bit-parallel design.

2008-04-04: Master Thesis Presentation

Published: 2008-04-03

Tomorrow 10.15 in E:2311, Julia Alegre Rubio [alegre.rubio84@gmail.com] will present her Master’s thesis with the title "Multiuser MIMO in an indoor office scenario".

Thesis Objetives:
=================
The objective of this thesis is as follows
• To study the MIMO channel properties and evaluate standard channel parameters
• To design interpolation algorithms for channel estimation
• To study possibilities for Multiuser MIMO-OFDM

Outline of the Thesis
The thesis is organized as follows:
• Chapter 2 presents a description of the channels for the two data files used to perform this project. Then the most important standard paramenters are discussed in details.
• In Chapter 3, the two-dimensional interpolation using the pilot-symbols and Wiener filtering is carried out. This option has been chosen as the best suitable. Some options are considered in order to improve the efficiency or the user handling.
• Chapter 4 presents and studies the results obtained in the previous chapter for the two data files provided. Differences between them and limitations to perform the interpolation are investigated.
• Chapter 5: Study of possibilities for Multiuser MIMO-OFDM. Application of Beamforming to increase the SINR.
• Finally, some conclusions are drawn in Chapter 6.

Exjobbspresentation 2008-03-26

Published: 2008-03-12

Silvia Sadaba presenterar sitt exjobb onsdagen den 26/3 klockan 10 i E:3139. titel. "Impact of Metric choices for reduced complexity detection of multiple antenna systems"

Handledare: John B. Anderson och Fredrik Rusek

Dissertation 18-3-2007

Published: 2008-02-04

Eligijus Kubilinskas defends his doctoral thesis "Design of multi-layer telecommunication networks: fairness, resilience and load balancing" at a public dissertation Tuesday 18th of Marsch 2008 at 13.15 in E:1406. Faculty opponent is Dr. Tibor Cinkler, Budapest University of Technology and Economics.

Abstract:
=========
Migration to Next Generation Internet architectures poses new challenges for network operators in planning core networks and calls for efficient network planning and optimization tools. Optimization models underlying such tools are developed in this thesis. We study a number of single and two-layer core network design problems defined as mathematical programmes, focusing on fair bandwidth allocation among demands, recovery mechanisms, and load balancing on network links.

Assuming elastic traffic, fair allocation of network bandwidth among the users is not trivial since different users may have different preferences and requirements for minimum bandwidth. We study single and two layer network dimensioning tasks where elastic and non-elastic demands are combined. Application of different fairness principles is studied, with special attention devoted to proportional fairness. The models are developed for designing the networks for the normal state of network operation, as well as for failure states.

For the two-layer problems it is not at all clear in which layer the recovery should be performed, and what recovery mechanisms to use. Therefore, recovery aspects in different layers are studied and models are provided for different recovery mechanisms. Furthermore, a generic resolution framework and heuristic algorithms for the selected dimensioning and allocation problems in two-layer networks are developed.

Balancing of load on network links decreases probability of rejection of future requests due to shortage of resources in some parts of the network. In the thesis different load balancing options are discussed, and an integrated routing, recovery, and load balancing strategy is developed. It combines failure dependent backup path protection, shortest path routing, and load balancing according to proportional fairness principle.

The thesis presents both theoretical findings, models, and resolution algorithms for the studied problems. Efficiency of the algorithms is illustrated by numerical examples. The thesis also gives a systematic view and classification of different aspects related to network architecture, recovery, fairness, and congestion/flow control.

Exjobbspresentation 2008-03-18

Published: 2008-03-14

På tisdag den 18/3 kl 10.15 redovisas exjobbet "Methods for finding delaminations in composite sandwich structures" som gjorts i samarbete med Kockums och är utfört av Ola Svensson, i E:2311.

Florian Hug´s diploma thesis presentation 2008-03-18

Published: 2008-03-17

If you ever wanted to see a convolutional code with really IMPRESSIVE free distance, do not miss the presentation of Florian Hug's diploma thesis!

Where? E:3139
When? Tuesday, March 18 at 15:15

Abstract:
=========
Today’s communication systems demand increasing capacities but simultaneously decreasing error probabilities in order to provide fast and reliable data transfers. Therefore, channel coding, using proper codes with good error-correcting probabilities, like large free distances, has to be applied.

In this thesis, focusing on convolutional codes, different distance properties like the column distance, row distance, and, the most important one — the free distance — are presented. Exploiting the first two distances in the rejection rules together with the BEAST (Bidirectional Efficient Algorithm for Searching code Trees), code searches have been performed.

Existing tables of optimum free distance (OFD) convolutional codes and optimum distance profile (ODP) convolutional codes have been extended.

Several new codes were found with larger free distances than previously known codes of the same rate and complexity. In particular, new tables for rate 1/2 convolutional codes of memories up to 25 and rate 1/2 ODP convolutional codes of memories up to 40 are presented.

In the second part of this thesis, so-called woven graph codes, obtained by combining hypergraph-based codes with constituent convolutional codes are introduced. These woven graph codes are specified by their parity-check matrices and since their complexity can be rather large, an efficient method for obtaining their minimal-basic encoding matrices in minimal span form was implemented, as this form is suitable for the BEAST.

The thesis concludes by presenting promising examples of woven graph codes, with their free distance calculated by an optimized version of the BEAST. For example, in case of a rate 5/20 woven graph code with overall constraint length 67, its free distance of 120 was verified. Such woven graph codes are of particular interest since they provide good error correcting capabilities while being iteratively decodable.

Master Thesis Presentation 2008-03-14

Published: 2008-03-14

Ignacio Garcia Dorado will present his Masters thesis "Focused Crawling: algorithm survey and new appraches with manual analysis" today at 10:15 in E:3139.

Master thesis presentation 14/3 2008

Published: 2008-03-14

Welcome the Master's thesis presentation of Tommi Larsson and Yusheng Liu, "A Study of EDCA and DCF in Multihop Ad Hoc Networks", today at 13.15 in E:3139.

Abstract: The IEEE 802.11 based Wireless Local Area Network (WLAN) and ad hoc networks have been widely used and still continuously attract more and more interest. In recent years, along with the development of information technology, the requirements on the size of network, the speed of connection and the complexity of application are growing very quickly. Thus the Quality of Service (QoS) issue is paid much attention by researchers to achieve better performance in WLAN and ad hoc networks. The IEEE 802.11e standard which provides QoS enhancement in the original IEEE 802.11 legacy was released in 2005. In this thesis, the aim is to analyze the QoS performance gain provided by Enhanced Distributed Channel Access (EDCA) of IEEE 802.11e in ad hoc network compared to the original IEEE 802.11 standard, and the impact of changing low priority traffics on high priority traffics. Protocols are implemented in Network Simulator 2 (ns-2) to simulate the network and communication procedures.

2008-03-10: Final Project presentation

Published: 2008-03-05

On Monday 10/3 at 10.15 the Final Project "Waveform Typification and Quality Assessment in Atrial Fibrillation Analysis" is presented in E:3139 by Sara Jönsson and Simon Lund.

International postgraduate course on integrated wireless transceivers

Published: 2008-02-15

The first lecture in this course will be given 2008-02-21.

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Dissertation 2008-02-14

Published: 2008-01-15

Henrik Persson will defend hist doctoral thesis "Inter-System Handovers in Heterogeneous Wireless Systems" at a public dissertation Thursday 14/2 2008 at 10:15 in E:1406.
Faculty opponent is Dr. Ian Oppermann from Nokia Siemens Networks, Finland.

Abstract:
=========

To better utilize existing wireless systems, they can be combined together to interact and thereby provide better balanced capacity. They can further profit from this by getting their ongoing connection moved from the current system to another. The main issues are to make this move without losing the ongoing connection and to make it seamless, i.e., without the user noticing it. This action of moving an ongoing connection between different wireless systems is called inter-system handover. To make the inter-system handover the mobile terminal in use must support both the involved systems. By using the mobile terminals possibility to change system, the user can increase, e.g., the coverage, the bandwidth and the capacity. When using inter-system handovers the cost of the connection can also be optimized depending on the actual cost of using a specific system. Since the user in advance can choose the settings of the involved parameters, a specific operator or wireless system could be given priority when several alternatives exist.

To easier identify and understand the handover procedure it has been categorized and divided into classes. This new handover terminology structure is presented in one section of the thesis. The different types of handovers are divided into classes and presented with a short description. For example, one class is called initiation. Within this class the handovers are then categorized as network initiated, i.e., the network initiates the handover, and mobile initiated which indicates that the mobile initiated the handover.

Further, several investigations on wireless hierarchical structures are presented. The focus is on the inter-system handovers made between the different levels. Hierarchical structures with both two and three levels of wireless systems have been analyzed. They are performed to understand how the results change when a smaller area is compared with a larger that supports more types of wireless systems. The investigations are made with different parameter settings to obtain a more thorough base for conclusions. The results obtained in this thesis are very useful both from the view of a user and from an operators point of view. They would be beneficial when the user should set his parameters and/or for the operator planning the networks and their individual architectures.

Master Thesis Presentation 2008-02-08

Published: 2008-02-06

On Friday Februari 8th David Petterson presents his master thesis 'A comparative study of HD Photo and JPEG'.

Place: E:2311
Time: 11.00

Abstract:
=========
The need for improved image coding is growing due to the increase in resolution and quality of images produced by camera phones. The present de facto standard in image coding is the JPEG format [Ghanbari, 1999], which is based on compression technology more than twenty years old. In theory does HD Photo provide better compression ratio and lower distortion than JPEG, and moreover o ering advanced features such as region of interest decod- ing and fast downscaled decoding [HD Photo DPK.]. Besides, Scalado has already solved several of the standard JPEG shortcomings, providing full random access as well as high decoding performance when decoding downscaled images. This master's thesis is carried out as a comparative study of HD Photo in contrast to RAJPEG/JPEG. RAJPEG, Random Access JPEG, is an implementation of base- line sequential JPEG that provides full random access each coded unit. The aim of the thesis is to determine the value, from a technological and innovative standpoint, of implementing HD Photo in a camera phone, moreover to create an understanding of HD Photo and facilitate its implementation.

NEXT WIRELESS CENTER SEMINAR 2008-02-07

Published: 2008-01-31

NEXT WIRELESS CENTER SEMINAR
Thursday, 7 feb., kl. 15.15 in E:3139
Development Trends of Small Antennas for Mobile Terminals
Pertti Vainikainen
Professor, Radio Engineering
Helsinki Univ. of Technology

Abstract: We discuss recent developments in the area of small antennas for multi-system mobile terminals. The main challenge is to fit the antennas of over 10 radios into a small portable device together with other submodules like a large display, camera, and battery. In some future systems also multi-antenna configurations should be used. Mainly, the solutions in the talk are based on the so-called non-resonating coupling element technique developed at TKK. With this technique it is possible to reduce the size of the antenna elements significantly.

ExJobb presentation on E-paper 2007-02-01

Published: 2008-02-01

ExJobb presentation by Joe Evans and Sajjad Haider
Friday 1 February at 10:15 in E:3139

Abstract: Mobile devices require displays that are effective under any lighting conditions, have a wide viewing angle and consume little power. Reflective displays are a candidate for such products, and a number of novel technologies have been recently announced. Overall it has been suggested that reflective displays will change the world of digital assistants in the E-market, but the killer application is still to be developed. The project is divided into two parts. In the first part, the requirements for mobile devices based on reflective displays are extracted from a number of case studies. We look at the potential of the display technologies as well as the characteristics of application areas that differ in content and means of access. This way both commodity and top-of-line products will be identified. In the second part we select one case and detail a typical product such that the design, development and assembly costs will become quantified. Finally our results should allow the identification of potential killer applications and the validation of its near-future commercial outlook.

NEXT WIRELESS CENTER SEMINAR! From Electrostatics to UWB and MIMO Antennas

Published: 2008-01-24

Mats Gustafsson, Lektor, EIT Department, will give a lecture on Thursday 31 jan., kl. 15.15 in E:2311 (Orangeriet)

Abstract:
=============
There is an increasing demand for physically smaller and more advanced antennas in modern wireless communication systems. Design and optimization of these are very challenging. We give an overview of the theory, challenges, and opportunities associated with the design of small antennas. Specifically, several new identities and bounds for antennas are presented. Properties such as bandwidth and directivity are shown to be related to the low-frequency, i.e. electrostatic, behavior of the antenna. The theoretical results are illustrated with resonant as well as UWB antennas and some extensions to MIMO antennas are presented.

Masters Thesis Presentation, 31/1 at 13.15, E:2311

Published: 2008-01-31

Henrik Ramberg will present his master thesis "Investigation of the High Dielectric Feed (HDF) Antenna" 31/1 at 13.15 in E:2311

Abstract
========
The Planar Inverted F Antenna (PIFA) has mainly been used since the mobile phones began to have built-in antennas. With the new demands on the mobile phones the PIFA concept could need improvements.

This master thesis focuses on an alternative to the PIFA; the High Dielectric Feed (HDF) antenna. The HDF antenna differs to the PIFA in one essential way; the feed structure. A PIFA has a simple galvanic feed leg that is connected between the feed pad and the radiator. In a HDF antenna the feed leg is connected to a resonator that is located under the radiator in the antenna. The energy is delivered to the radiator from the resonator through coupling. Compared to a PIFA the HDF antenna has shown to be less sensitive to interfering Perfect Electrical Conductor (PEC) objects near the radiator of the antenna. In previous investigations it has also been shown that it is possible to create larger bandwidth for HDF antennas.

This master thesis has two main goals; first explain the behavior of the HDF antenna theoretically, secondly, create design rule recommendations for a HDF antenna.

The investigations are mainly performed using the simulation program CST Microwave Engineering Studios. Regarding the theoretical behavior of the HDF antenna, the investigations are to compare E- and H-field plots from CST. For investigations of the E- and H-field components of the coupling volume, the self developed Matlab program Hotspot is used. Hotspot plots 3D fields imported from CST in 2D-cuts. To reach the second goal, changes are made to the HDF antenna key components and the return loss results are evaluated.

One of the models that have been used in the simulations is built. The measurement result from this model is compared with an equivalent simulated model to evaluate the reliability of the simulation method.