Course Information
The objective of the course is to describe structured methods for construction of digital systems, based on the concept of state transition graphs. The state transition graph is a powerful tool when building a model of the system. This model can then be realised by a sequential machine, which is a realisation with logic circuits and delay elements. It is central to the course to understand the concept of state transition graphs and how different methods can be applied in the realisation chain so the resulting circuit has few gates, which leads to a hardware with small chip area.
Course code: EIT020
Credits: 9 hp
Activity terms: HT1 and HT2
Lecturer and examiner: Thomas Johansson
Course secretary: EIT's studentexpedition (Marianne Greiff Svensson)
Students: Compulsory for D2 and E2; Optional for F2 and C3.
Examination: Written exam and laboratories
