Introduction:

The lab assignments demonstrates some fundamental aspects of mixed mode simulations and modeling and they introduce CAD tools and simulators commonly used in research and development. The lab allows you to investigate different A/D converter architectures and some of their properties.

There are 3 assignments:

1. Modeling and studies of ADC fundamentals. (MATLAB) (20 hours)
2. Analog modeling with Verilog-A. (Cadence) (20 hours)
3. Modeling and simulation of a 5 bit flash ADC and an 8 bit pipelined ADC. (Cadence) (20 hours)

The assignments are rather extensive. The time required to solve them is approximately 60 hours. That means that the supervised hours (16h) will not be enough and that work outside supervised hours will be inevitable! Be well prepared with preparations and questions at the supervised hours !!

Slides, manuals and design files:

The lab manual will be handed out at the lab seminar. Below you can download the additional material you need for the three assignments:

 Assignements - Seminar slides
 Assignment 1+3 - Matlab files
 Assignment 2 - Cadence files, VerilogALab.zip
 Assignment 3 - Cadence files, SpectreVerilogLab.zip

Requirements for pass degree:

Ph.D students work individually.
Undergraduate students work in groups of 2-3 persons.

In order to pass this lab course, each group of students shall hand in one lab report with simulation results, schematics and answers to questions given in the lab manual. The lab report must be one document, handed in in hardcopy. 

All undergraduate students must attend at least 3 of the 4 supervised sessions.

DEADLINE!! One assignment report containing all three assignments shall be handed in before 14/12.

Assignments supervisor:

The scheduled hours (12h) are supervised by D. Radjen and Xiaodong Liu.