Approved
Design of a 30 GHz PLL for use in Phased Arrays
Byron Murphy (2014)
Start
2015-11-18
Presentation
2016-06-14
Location:
Finished:
2016-06-14
Master's thesis:
Abstract
Supervisor: Johan Wernehag (EIT) and Henrik Sjöland (EIT)
Examiner: Pietro Andreani (EIT)