Approved
Turbo decoder with early stopping criteria
Henrik Ljunger (2010)
Start
2015-07-01
Presentation
2016-05-27 13:15
Location:
E:2311
Finished:
2016-11-22
Master's thesis:
Abstract
The aim with this Master’s thesis work is to implement a fully verified turbo decoder in hardware on a FPGA. The decoder should meet all the LTE requirements for performance and latency and use the Max-Log-Map approach. The main goal is to investigate the potential energy savings from implementing a technique to stop updating of code-words as soon as the reliability is above a certain threshold. This will potentially lead to savings in calculations and in number of memory accesses which in turn should lower the energy consumption. The approach will be to divide the implementation in three parts. First the Max-Log-Map sub-module will be implemented and verified. Then the interleaver and de-interleaver will be implemented and connected to create a functional turbo decoder using the Max-Log-Map approach. Finally the early stopping method will be implemented and tested. The system will be designed with the high level synthesis tool Catapult.
Supervisor: Muris Sarajlic (EIT) and Joachim Rodrigues (EIT)
Examiner: Liang Liu (EIT)