Approved
Modeling And Implementation of All-Digital Phase-Locked Loop Based on Vernier Gated Ring Oscillator Time-to-Digital Converter
Ji Wang (2012)
Start
2014-02-01
Presentation
2014-10-23
Location:
Finished:
2014-10-23
Master's thesis:
Abstract
Supervisor: Ping Lu (EIT)
Examiner: Pietro Andreani (EIT)