Approved
Efficient High-level Synthesis Implementation of massive MIMO Processing on RFSoC
Sijia Cheng ()
Start
2021-10-12
Presentation
2022-03-17 13:15
Location:
E:3139
Finished:
2022-03-29
Master's thesis:
Abstract
This thesis project targets for FPGA prototyping of Beyond 5G wireless communication systems based on massive MIMO and large intelligent surface technologies. More specifically, the project will explore the use of high-level synthesis for efficient implementation of uplink massive MIMO detection algorithms. Analysis on development time, area consumption, throughput will be performed, including the trade-off among these design metrics. At the end of the project, the implementation will be demonstrated on Xilinx RFSoC boards.
Supervisor: Liang Liu (EIT) and Steffen Malkowsky (EIT)
Examiner: Erik Larsson (EIT)