This is the full design kit for the United Microelectronics 130nm
process.
Access to this kit is restricted to those in the cccd group.
For those of digital persuasion we have a cell library from Faraday Technology.
The environment can be initialized and started by the
commands
tde> source ~umc/setup
# Use the new umc_setup8 instead!
tde> icfb &
As usual this will also copy some setup files and a previously
empty directory should be used.
New (Cadence)libraries shoul be attached to the 'umc13mm'
technology.
Schematic drawing and simulation works fine. Layout can be drawn
but neither tested nor
extracted yet.
There is a lot of ducumentation, start with these (someone out there
loves long filenames)
$UMC_DIR/doc/
GT-DBT-030806-001_Ver.2.2.pdf
# Kit Manual G-02-MIXED_MODE_RFCMOS13-1.2V_3.3V-1P8M-MMC_FSG_L130E-EDR.PDF
# Proc. Params G-03-LOGIC13-1.2V_3.3V-1P8M-HS-TLR.pdf
# Design Rules G-03-MIXED_MODE_RFCMOS13-1.2V_3.3V-1P8M-MMC_L130E-TLR.PDF
# More
Rules G-1B-077.PDF
# Metal Rules G-04-MIXED_MODE_RFCMOS13-1P8M-MMC_FSG-INTERCAP.pdf
# Cap. Values G-05-MIXED_MODE_RFCMOS13-1.2V_3.3V-TWIN_WELL_MMC_L130E-SPICE.PDF
#
Sim. Info G-05-MIXED_MODE_RFCMOS13-1.2V_3.3V-TWIN_WELL_MMC_NOISE_L130E-SPICE.PDF
# Noise G-06-MIXED_MODE_RFCMOS13-1.2V_3.3V-1P8M-MMC_L130E-MASKTOOL.PDF
#
Mask Info
$UMC_DIR/TwinWellModels/*.pdf
# More documentation of the models.
New RF library ( v1.1 P1 )
The new RF library will be defined correctly for new users. Old users
have to make sure that the definition
of the technology library, to which own libraries should be attached,
in the 'cds.lib' file looks like this
DEFINE umc13mmrf $UMC_DIR/MM_RF/umc13mmrf
In order to run the LVS checker some further modifications has
to be made in the 'cds.lib' file.
Change all '$CDS_INST_DIR' to '$CDSDIR'.
Remove the line starting with 'DEFINE avTech ... '.
The environment should be initialized and the program started by
the commands
> source ~umc/umc_setup8
> icfb &
More info can be found in $UMC_DIR/MM_RF/models/Rf/L130E_RFCMOS_model_v1.1p1.pdf
Quick LVS guide
Pins in the layout view has to be created as text labels ( Create >
Label ) in the same layer as the structure on
which it is put. Make sure it is completely enclosed by the wire or rectangle.
When LVS is started ( Assura > Run LVS ) a form will pop up.
Make sure that the settings for the schematic
and layout source are correct. 'RunName' is the base name for all
the files that will be produced.
Design Rule Check
The DRC is initiated by the command Assura > Run DRC from
the layout window. The form that pops up is
initiated for interactive check from the database (DFII). Make sure that
the cell specification is correct and se-
lect a Run Name. The Run Directory tells Assura where
to put all log-files. This directory can grow very
big and should be cleaned up once in a while.
The Switch Names can be modified for specific needs. More information
about these can be found in the file $UMC_DIR/G-DF-MIXEDMODE_RFCMOS13-1.2V-3.3V-1P8M-MMC_L130E-Assura-drc-1.1-p2.rul
When the form is filled out satisfactory click on Apply and wait
for it to finish. The error viewer is quite easy
to use and should not require any instructions.
It is still not recommended to use the MIMCAPS_MML130E capacitors
due to the lack of simulation models.
Old stuff below, don't read !
There is also an RF library available. This can be utilized
after the following definition has been
inserted into the local cds.lib file.
DEFINE umc13mmrf $UMC_DIR/umc13mmrf
This is a technology library, so attach your own libraries to this one.
In order for the simulator to find these models a new .cdsinit file
must be copied from $UMC_DIR .
Also, have a peek at $UMC_DIR/rfmodels/L130E_RFCMOS_model_v1.0p1.pdf
Do not use the MIMCAPS_MML130E structures. There are no simulation
models for them. Use MIMCAPS_RF instead.