STMicroelectronics 65nm CMOS v5.3.4
[Feb 2011]
This is the newest design kit for the STM 65nm standard cmos process.
The
older version
should not be used anymore.
There is also a special
RF design kit
of older version elsewhere.
This page contains instructions on how to use the kit together
with the analog
design tools on the
Linux platform only. For use with
the synthesis tools, have
a look
here for a short
description.
Notes
- Only basic schematic and simulation have been tested so
far
- Old Cadence (v5.1.4) is the one used
If the digital libraries do not appear in the Layout Manager:
remove the file '.ucdprod'
and rerun the setup script.
Setup procedure
The environment is defined by a setup script
which is called by the command
>
source /usr/local-eit/cad2/cmpstm/stm065v534/setup
The first time this is run, the script will also
copy some files that are necessary for proper
function of the design kit. Afterwards the
Cadence design tool can be started by
> icfb &
Connect new libraries to technology
cmos065 .
Simulation is a little more complicated than
usual. Start the procedure
by the command
Tools > Setup Corners from the
Analog Environment
window. Here, the wanted model files can be selected.
After the selection
has been confirmed by
Save Model File the simulation
can be run
normally. See more in the documentation
!
Documentation
There is also an extensive set of maunuals which can
be read by a browser which
is started by the command
>
unidoc &
Cadence Documentation
The documentation viewer can be started directly from the tool or by one
of the following commands
$CDS_INST_DIR/lnx/tools/bin/cdsdoc # Cadence Main Tool
$MMSIM/tools/bin/cdnshelp
# Analog Simulator
$SOCDIR/tools/bin/cdnshelp
# Place and Route
$LDVDIR/tools/bin/cdnshelp
# Digital Simulator
$ASSURAHOME/tools/bin/cdsdoc # Assura DRC,
LVS, and Extraction
Extra Pads
There is a set of smaller rf-pads built by Carl. They can be accessed
after including the
following line in the
'./cds.lib' file.
'DEFINE CBlib065 /usr/local-eit/cad2/cadence/CBlib065'
Chip Assembly Router
The Autorouter is now available from the
Layout XL tool (
Routing
> Autorouting).
The mauals for this can be read by
$ICC/share/bin/cdsdoc .
Design Rule Check
It is now possible to verify that the layout rules for the
design are fulfilled. This is done
by the tool
Calibre from
Mentor Graphics.
It is started from the
Calibre menu header
in the layout window. If this does not exist, try removing
the local
.cdsinit file and redo
the initialization procedure where an new file wiil be created.
After selecting
Run DRC in the
Calibre menu
two new windows are created. In the one
labeled
Customer Settings some switches that affect
the checking can be modified. From
the other,
Calibre Interactive, the drc run can be
started with the button
Run DRC. The
errors are then presented in an easy to use viewer.
Calibre LVS
Calibre > Run LVS will start
Calibre for a
Layout
versus Schematic check. Here a
netlist created from the schematic view will be compared to an extracted
netlist from the
layout. All component sizes and connections will be compared and discrepancies
reported.
Under
Rules check that
$U2DK_CALIBRE_LVS_DECK is filled
in. At
Inputs infor-
mation of the cell to be tested can be found.
Run LVS will start the check.
Global power nets, like vdd!, will confuse Calibre and will be reported
as wrong.
Select the button
Ingore layout and source pins ... at
LVS
Options : Supply to avoid
the problem with the global supply nets.
Calibre PEX
The
Parasitic EXtraction will calculate
the parasitic components on the layout and
create a
'calibre' view that can be simulated in order to gauge
their impact on the design.
Select
CALIBREVIEW and
Names From LAYOUT at
Outputs.
The type of extraction
(R, L, C) can also be chosen here.
The resulting view (
calibre) can then be used by a config test
bench as usual.