ST Microelectronics 65nm RF CMOS v5.3.4

[Feb 2011]
This page describes how to use the new RF design kit for analog design.

Do not use the older version for new fabrications.

The access to this PDK is very restricted so it is only available from the Linux computer
named 'radiocad' or the newer 'marconi'. People without a local account on these machines
can not use this design kit.

It is still the old Cadence 5.1.41 that is used.


Setup procedure

The environment is defined by a setup script which is called by the command

> source /home/radiocad/cmp/c65rf534/setup


The first time this is run, the script will also copy some files that are necessary for proper
function of the design kit. Afterwards the Cadence design tool can be started by

> icfb &


Connect new libraries to technology cmos065 .

Simulation is a little more complicated than usual. Start the procedure by the command
Tools > Setup Corners from the Analog Environment window. Here, the wanted model
files can be selected. After the selection has been confirmed by Save Model File the si-
mulation can be performed normally. See more in the documentation!


Documentation

There is also an extensive set of maunuals which can be read by a browser which
is started by the command

> unidoc &

Then click on DK_cmos065lpgp_RF_7m4x0y2z_2V51V8 5.3.4   f. ex.

Hopefully the setup files will make sure that the web browser is started automatically but the
location of the pdf reader, '/home/radiocad/cmp/c65rf534/Unidoc_2.7.c/bin/acroread',
has to be fed in.

Extra Pads

There is a set of small rf-pads created by Carl. They can be accessed after including the
following line in the 'cds.lib' file.

'DEFINE CBlib065 /usr/local-eit/cad2/cadence/CBlib065'  (local-tde on radiocad)



Calibre Design Rule Check

It is now possible to verify that the layout rules for the design are fulfilled. This is done
by the tool Calibre from Mentor Graphics. It is started from the Calibre menu  header
in the layout window. If this does not exist, try removing the local .cdsinit file and redo
the initialization procedure where an new file wiil be created.

After selecting Run DRC in the Calibre menu two new windows are created. In the one
labeled Customer Settings some switches that affect the checking can be modified. From
the other, Calibre Interactive, the drc run can be started with the button Run DRC. A
stream file will now be created from the information in the layout. The drc will then be
applied to this data file.

The errors are then presented in an easy to use viewer.


Calibre LVS

Calibre > Run LVS will start Calibre for a Layout versus Schematic check.  Here a
netlist created from the schematic view will be compared to an extracted netlist from the
layout. All component sizes and connections will be compared and discrepancies reported.

Under Rules check that $U2DK_CALIBRE_LVS_DECK is filled in. At Inputs infor-
mation of the cell to be tested can be found.

Run LVS will start the check.

Global power nets, like vdd!, will confuse Calibre and will be reported as wrong.

Select the button Ingore layout and source pins ... at LVS Options : Supply to avoid
the problem with the global supply nets.


Calibre PEX

The Parasitic EXtraction will calculate the parasitic components on the layout and
create a 'calibre' view that can be simulated in order to gauge their impact on the design.

Select CALIBREVIEW and Names From LAYOUT at Outputs. The type of extraction
(R, L, C) can also be chosen here.

The resulting view (calibre) can then be used by a config test bench as usual.