far130lnx.html

Faraday libraries for UMC 130nm process - Linux.

This is a short description on how to synthesize, simulate, and place&route a design with
the digital libraries from Faraday.

More information regarding the process itself can be found at UMC 130nm.
The tools that will be used are

Synopsys Design Compiler : Design Synthesis
Mentor Graphics ModelSim : VHDL and Verilog Simulation
Cadence Encounter : Place and Route.

The setup scripts have been modified to utilize the latest versions of Synopsys v2009.06
and ModelSim 6.5c. If the older setup (before Feb 2010) is required, use setup2007
instead of allsetup.

There is an even newer setup-script that utilizes more modern versions of both Synopsys
(v2010) and ModelSim6.6. It is for the moment only available on the department and bears
the name of setup2010. These newer versions should work as described below.

In this newer script is also added the tools Synopsys VCS2010 and Cadence ETS9.12.

Due to a license update the place and route tool 'encounter' is no longer available.
Instead use the command 'velocity' to start.

Setup

All the tools needed are initialized by one command which should be run in an empty sub-
directory. A lot of setup and example files will be created if they do not already exist.

> source /usr/local-eit/cad2/far130/allsetup

If on the laboratory computers use the following command instead

> inittde dicp10

The setup routine will create a file structure that will look like this

                                             StartDir
       ______________________|___________________
       |                    |                      |                     |                |
    vhdl          netlists          WORK          work          soc

Use StartDir as default location when running Synopsys or ModelSim. Before using the
Encounter tool, descend into the library soc. The function of the other directories are

vhdl : folder for vhdl-files.
netlists : output files from synthesis
work & WORK : storage libraries for ModelSim and Synopsys.

Memory Compiler

The Faraday memory compiler (v200901) for the Low leakage version of the process is
also made available by the startup script. The main gui is then started by the command 'memaker'.

Some documentation can be found in the directory $FTC/doc .

Synthesis with Synopsys

Currently, only one library is available. It is of the low leakage kind and contains both
standard cells and Input/Output pads. The search path is specified in the local file
'.synopsys_dc.setup'.

fsc0l_d_generic_core_<opt>.db & lib : Low Leakage , Standard Cells
foc0l_a33_t33_generic_io_<opt>.db & lib : Low Leakage, IO Cells
fsc0h_d_generic_core_<opt>.db & lib : High Speed, Standard Cells
foc0h_a33_t33_generic_io_<opt>.db & lib : High Speed, IO Cells

The timing options are

ff1p32vm40c : Fast,
ss1p08v125c : Slow,
tt1p2v25c : Typical,

More documentation of the libraries can be found in the directorys $FAR_LIB/fsc0l_doc,
foc0l_doc, fsc0h_doc, and foc0h_doc.

The synthesis program is started by the command design_vision .

There is a small example that can be studied. Use 'source comp.dv' to start.

Manuals for the syntesize tools can be found at this web page

file:///usr/local-eit/cad2/synopsys/FEVdocs/FEVsuite.html

Note: PrimeTime is now started by the command 'pt_shell -64bit'

Simulation

Simulation is performed in the ModelSim tool, which can handle both vhdl and verilog
files. Simulation can be executed before or after synthesis. The simulator tool is started by the
command 'vsim'.

There is a small example command file that runs through an entire simulation. This is executed
by typing 'vsim -do medfilt.cmd' at the shell prompt.

There is a lot of documentation available from the tool menues. Here is a direct address to a
tutorial $MODEL_SIM/docs/pdfdocs/modelsim_se_tut.pdf

Place'n'Route

The place-and-route of the construction is performed by the Cadence tool Encounter.

It is started with the command 'encounter' from the library 'soc'. Do not use an ampersand (&) here.
The window from which Encounter is started will serve as the command input window.

The setup command will copy some setup- and command files that executes an example design
in Encounter. The entire session is then launched by the command 'source MedFilt.com' from
the command window. Naturally the commands are also available from the tool menues.

As shown in the example pad placement file 'MedFilt.io' the corner- and power pads can be in-
troduced in this file. There is no need to edit them into the verilog file.

Exporting Design

When the design is ready, it has to be transfered into the layout editor (dfII) for final fixing up, bond-
pads have to be added. The pads used do not contain any bonding area. DRC checks must also be
executed. The transfer of the design is done by exporting a stream file, which describes the entire
design with placement of the cells and all routing information, from Encounter.

Invoke the command Design > Save > GDS and fill in the name of the stream file to be created.
For mapfile, use faraday_soc.map, which resides in the local directory from which Encounter is
started.