UMC 130nm Design Kit for Linux Platform

This is the full design kit for the United Microelectronics 130nm process.

This page describes how to initialize the design environment and start the Cadence tool
for schematic and layout design.

There are a number of digital libraries from Faraday for this process. These can be used for
synthesis of digital designs by Synopsys. More information abot this here.



Setup


From the department domain the environment is initialized by the command

> source  /usr/local-eit/cad2/umc/umc130/setup

If instead on the laboratory computers use

> inittde  umc130lnx

( There is a special version set up for use with the GoldenGate simulator. This is defined
by typing 'inittde umc130lnxgg' instead.)


When this is done the tool is then started with

> icfb &



As usual this will also copy some setup files and a previously empty directory should be used.
New (Cadence)libraries should be attached to the 'umc13mmrf' technology.

Documentation

In the library '$UMC130/docs/' there are a lot of manuals.

G-03-MIXED_MODE_RFCMOS13-1P8M-MMC_L130E-TLR-Ver.2.4_P1.pdf                # Design Rules
G-03BE-GENERATION13-TLR_BEOL-Ver.2.3_P1.pdf                                                        # More Rules
G-02-MIXED_MODE_RFCMOS13-1P8M-MMC_FSG_L130E-EDR-Ver.2.3_P1.pdf      # Process Params.


Information regarding the design kit can be found in the library $UMC130 .

G-9FD-MIXED_MODE_RFCMOS13-1P8M-MMC_FSG_L130E_UM130FDKMFC-FDK-Ver.B05_PB.pdf
FDK_Application_Note_UM130FDKMFC_B05_PB.pdf
FDK_User_Guide_V1_1.pdf
Release_Note_UM130FDKMFC_B05_PB.pdf


Design Checks

For design verification the Cadence Assura tool is used. If there is a menu-header labeled Assura
in the layout editor, the tool is avaiable. If not, help should be requested.

Design Rule Check

Select Assura > Run DRC in the layout window. Then choose Technology umc130_drc in the window
that pops up. Also set Rule Set to either 1P8M2T or 1P8M2T20kA depending on the fabrication option.
A number of  runtime Switches that modifies some checks can also be set.

Select a Run Directory where the data- and log-files can be stored by the Run Name. Remember
that big designs implies big data sets.

When all is filled out, hit Apply !

The errors will then be presented in an easy-to-use browser.

There is also an extra Rule Set named xcheck that currently only checks for overlap of the implant layers
nplus and pplus. This rule has been introduced by IMEC and should be respected.

Quick LVS guide

Pins in the layout view has to be created as text labels ( Create > Label ) in the same layer as the
structure on which it is put. Make sure it is completely enclosed by the wire or rectangle.

When LVS is started ( Assura > Run LVS ) a form will pop up. Make sure that the settings for the
schematic and layout source are correct. Select Technology and Rule Set as above and click Apply.

Parasitic Extraction

Only after a successful lvs run can the parasitc components be extracted from the layout. Select
Assura > Run RCX to activate the form. Make sure that Technology and Rule Set are set correctly.
Set Output to Extracted View to create a new cellview (av_extracted) containing the reslut of the
extraction. Under the flap Extraction select Cap Extraction Mode to Coupled and type in 'gnd!'
at Ref Node.  Click on Apply and wait for it to finish.

If all works well the cellview av_extracted will now contain the result of the extraction. This can
be used in a post-layout simulation together with the hierarchy editor as usual.

Always finish with the Assura > Close Run command to shut down Assura in a proper way.

DRC with Calibre

It is also possible to run the design rule check with the Mentor Graphics tool Calibre.

From now on the setup script will also perform the initialization for  Calibre. In order for
this to work properly existing users must first remove their '.cdsinit' file before running
setup.

Use Calibre > Run DRC from the layout window. In the window that appears fill in at DRC Rules File
the location '$UMC130/RuleDecks/Calibre/DRC'. Then click on the button marked ... and select the
apropriate checking file. These are the required ones for the normal version of the process

'G-DF-MIXEDMODE_RFCMOS13-1P8M2T-MMC-L130E_Calibre-drc-2.5-P1'   : Lower Levels
'G-DF-GENERATION13-BEOL-1P8M2T-Calibre-drc-2.3-P3_20KA'                      : Metal Levels
'umc_ant_0.13um_1P8M2T-CALIBRE-DRC-P3.cal'                                                         : Antennas

Also fill in a library to store the files in.

Then start the checking by clicking on Start DRC.

There is a new rule introduced by IMEC. The implant layers nplus and pplus may not overlap. Since this is
not part of the design rules it is not checked for by the provided Calibre files. It can be checked by the Rule Set
xcheck in Assura as described above.




Mixed-Mode Design and Simulation

The standard cell libraries from Faraday are now available for design in the Cadence environment.
They show up in the Library Manager by these names

FOC0L_A33_T33_GENERIC_IO : Low Leakage, IO cells.
FSC0L_D_GENERIC_CORE        : Low Leakage, Standard Logic
FOC0H_A33_T33_GENERIC_IO : High Speed, IO cells.
FSC0H_D_GENERIC_CORE       : High Speed, Standard cells.

The libraries contain symbols and layout that can be used in the schematic and layout editors. Information
regarding  the libraries can be found on the digital pages  for this process. Since there are no schematic
views with transistor symbols for the library cells they can not be simulated by the spectre simulator.

In order to simulate a design with the libraries create a config view of the testbench and select the
spectreVerilog simulator among the templates. Then use this view to select how each cell is to be
simulated. The symbol view of the standard cell means that it will be simulated by the digital simulator.

Start the Analog Environment and set the simulator to spectreVerilog. Also check that the Options
File under 'Simulation > Options > Digital' is set to '/usr/local-eit/cad2/far130/syn2009/verilog.opt'.

The default Interface Elements (umc13mmrf:MOS12_..) have been set for 1.2V.


Importing Stream Files 

The place and route tool used (Encounter) gives it's output as a stream file. This can be imported
into the layout editor by the following procedure. The design can then be further edited and the
layout checked by the drc tool.

* Copy the Layer Map file, $UMC130/stream.map.
* Create a Cadence library in which to read in the design. Attach to 'umc13mmrf' technology!
* The command 'File > Import > Stream' will open up the stream in form. Input File is the file
   with the design. Type the name of the newly created library at Library Name. In the sub-form
   User-Defined Data fill in 'stream.map'. Under Options check Retain Reference Library and
   list the Faraday libraries used at Reference Library Order. Use space as separator. For instance
   'FSC0L_D_GENERIC_CORE FOC0L_A33_T33_GENERIC_IO'.
*  Click OK to execute and the design will appear in the selected library.

Adding Bonding Area


Since the pad cells in the Faraday libaries does not have any area for bonding, this has to be added.
A suitable one is the PAD8ML cell in the Low Leakage io-library. This can be done by adding these
bonding areas to the design and connect them to the pads.

An other way is tho use the composite pads in the XPAD09 library. These consist of a pad and the
bonding area placed together and connected by metal. They can be used by selecting a pad in the
layout and then changing the library reference to 'XPAD09' and adding a '_C' to the cell name, ie.
change XMLB to XMLB_C.


The available pads are VCC3ILB_C, VCC3OLB_C, VCCKLB_C, GND3ILB_C, GNDOLB_C,
GNDKLB_C, YA29SLB_C,  and XMLB_C from the Low Leakage library for 8kA top metal.
Also the High Speed pads VCC3IHB_C, VCC3OHB_C, VCCKHB_C, GND3IHB_C, GNDOHB_C,
GNDKHB_C, YA29SHB_C,  and XMHB_C have been added.

There is a second set of pads in the XPAD09 library. These have the suffix '_C20' and are intended for
use with the fabrication option '20 kA thick top metal'. This will probably be the most normal case.