DARE -- Digitally-Assisted Radio Evolution
2011-03-01 -> 2016-03-31
DARE targets the design of radio receivers for cellular communications complying with the LTE Advanced standard. A downlink data rate of up to 1Gb/s is addressed, with an aggregated signal bandwidth of up to 100 MHz. In addition to the larger signal bandwidth, a data rate boost is achieved by means of multiple-input multiple-output (MIMO) radios. Furthermore, compared to earlier standards, LTE Advanced allows the received signal to be present over two or more non-contiguous bands (so-called carrier aggregation), a feature that poses new challenges to the practice of radio design.
The power consumption in a typical LTE Advanced radio is going to be relatively high, and a power-aware design approach is called for. Apart from the obvious choice of state-of-the-art nanometer CMOS processes for circuit integration, the outstanding digital computation capability offered by such processes also enables the deployment of highly complex algorithms to save power while securing the radio performance, which is always, to some extent, limited by the imperfections of the analog circuits.
The results of the DARE research are expected to be of practical use already in the near future, while in the longer term they will help the Swedish industry to take up the challenge from the world players in the cellular radio business. Conversely, DARE benefits hugely from the interaction with experienced researchers from the telecom industry, which provide standardization and system-level information typically not available within an academic environment.
DARE has already obtained very significant results in the design of key building blocks of an LTE Advanced radio: wide-band low-noise reconfigurable receiver front-ends with high linearity; wide-band and low-phase noise VCOs; a digital PLL including novel PLL building blocks; wide-band, linear and digitally reconfigurable channel-select filters; a wide-band analog-to-digital converter based on a delta-sigma modulator; a complete receiver front-end together with a novel block merging the delta-sigma modulator within the channel-select filter; Matlab-based LTE RF and downlink simulators; a power-efficient channel estimation algorithm for OFDM systems; a fully digital approach to the removal of the leakage from the transmitter to the receiver in the radio; a reconfigurable digital baseband architecture for MIMO-OFDM applications; a power-efficient adaptive radio channel estimator; and an iterative MIMO detection and decoding receiver. A large number of analog and mixed-signal circuit prototypes have been designed and fabricated in a 65nm CMOS process, which has lately been replaced by a state-of-the-art 28nm FD-SOI CMOS process, available to DARE thanks to a collaboration with STMicroelectronics.
|Finansiär:||Stiftelsen för strategisk forskning (SSF)|