Lund Connected Systems and Circuit Design Workshop 2020
Welcome to the 2020 Lund Connected Systems and Circuit Design Workshop
When - preliminary:
10 September at 13.00 - 16.00
11 September at 9.00-12.00
The workshop will offer an overview of research activities in IC design and realted areas at Lund University.
The workshop is free of charge! Put please register at http://www.lth.se/digitalth/events/register-connected-systems-20-09-10-11/ in order to get an access link.
|När:||2020-09-10 09:00 till 2020-09-11 12:00|
|Plats:||Online (link registration)|
Economic optimization of the operation of energy production and district heating networks.
Speaker:Björn Malmström, CTO at Energy Opticon
DescriptionEnergy Opticon is one of the leading providers of software for combined production optimization of district heating and electricity. For a nice video, see https://youtu.be/0bVb1ynLZ_A
Zoom link: https://lu-se.zoom.us/j/65388766852
|När:||2020-06-16 13:15 till 2020-06-16 14:00|
PLDI 2020 Tutorial: Design Space Exploration - also broadcasted on Youtube
When: 15 June at 17.00 to 21.00 (8.00-12.00 PDT)
The registration is closed. Due to +1000 registrations the event will also be broadcasted at Youtube: https://youtu.be/0S-y7uCY93Q
Participants can ask questions on the Slack channel at the PLDI2020 Slack https://pldi20.sigplan.org/slackinvite
Real-world engineering problems commonly have multiple objectives that have to be tuned simultaneously. The trade-off Pareto front resulting from the tuning is used as a decision-making tool for selecting the best trade-off for any specific user scenario. Specifically, multi-objective optimization is a crucial matter in programming languages, compilers and hardware design space exploration (DSE) because real-world applications often rely on a trade-off between several objectives such as throughput, latency, memory usage, energy, area, etc. ?
While the growing demand for sophisticated DSE methods has triggered the development of a wide range of approaches and frameworks, none to date are featured enough to fully address the complexities of DSE in the PL/compilers domain. To address this problem, we introduce a new methodology and a framework dubbed HyperMapper. HyperMapper is a machine learning-based tool designed for the computer systems community and can handle design spaces consisting of multiple objectives and numerical/discrete variables. Emphasis is on exploiting user prior knowledge via modeling of the design space parameters distributions. Given the years of hand-tuning experience in optimizing hardware, designers bear a high level of confidence. HyperMapper gives means to inject knowledge in the search algorithm. The framework uses a Bayesian Optimization algorithm, i.e., construct and utilize a surrogate model of the latent function to guide the search process. A key advantage of having a model is the reduction of the optimization time budget. HyperMapper is a plug-and-play framework that makes it easy for compiler/hardware designers to explore their search spaces.
To aid the comparison of HyperMapper with other DSE tools, we provide a taxonomy of existing tools.
Programme details at: https://pldi20.sigplan.org/details/pldi-2020-tutorials/1/Design-Space-Ex...
To participate is free of charge.
The tutorial is part of the Programming Language Design and Implementation (PLDI) Online conference 15-20 June
|När:||2020-06-15 17:00 till 2020-06-15 21:00|
|Plats:||Online at the Zoom platform (Link by registration) and Youtube|
PhD Defence: Electrical Characterisation of III-V Nanowire MOSFETs (Markus Hellenbrand)
Titel: III-V Nanowires for High-Speed Electronics
Faculty opponent: Professor Tibor Grasser, TU Wienna
When: 12 June at 9:15
Location: E:1406, E-building, Ole Römers väg 3, LTH, Lund University / Zoom: https://lu-se.zoom.us/j/64523497259
Thesis abstract: The ever increasing demand for faster and more energy-efficient electrical computation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductor field-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.
This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.
The first part of the thesis focusses on the characterisation of electrically active material defects (?traps?) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities ? projected to the oxide/semiconductor interface ? of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.
Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.
Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits.
|När:||2020-06-12 09:15 till 2020-06-12 09:15|
|Plats:||E:1406, E-building, Ole Römers väg 3, LTH, Lund University / Zoom: https://lu-se.zoom.us/j/64523497259|
Lic. Thesis Seminar: On Lightweight Security for Constrained Environments (Jonathan Sönnerup)
Topic: On Lightweight Security for Constrained Environments
Presenter: Jonathan Sönnerup, Networks and Security, Department of Electrical and Information Technology at Lund University
When; 10 june at 13.15
Online location: https://lu-se.zoom.us/j/64369594441
Physical location: E:1406, E-building, Ole Römers väg 3, LTH, Lund University
Reviewer: Dr. Håkan Englund, Ericsson
Abstract: The market of connected devices, IoT devices in particular, is hotter than ever. Today, lightweight IoT devices are used in several sectors, such as smart cities, smart homes, healthcare, and the manufacturing industry. IoT solutions help increase productivity by predictive maintenance and resource management in the industry. Devices with voice interfaces are spreading rapidly in the home automation markets. Hospitals utilize these ``smart'' devices to monitor patients and present diagnostics data, aiding physicians in their work.
It is safe to say that we will be surrounded with more and more connected devices. This opens up to potential attacks, where adversaries may try to disrupt critical services or steal sensitive information. To combat this, data needs to be secured in different ways. This dissertation presents cryptographic algorithms and their performance in lightweight constrained devices.
First, a new lightweight cryptographic algorithm, Grain-128AEAD, is presented. Grain-128AEAD is a stream cipher designed to be implemented in hardware at a low cost while still being fast. The new design improves on earlier versions by making previous attacks more difficult.
Next, Grain-128AEAD is implemented in hardware using multiple optimization techniques to fit different criteria. Trade-offs between throughput, power, and area are evaluated to analyze the suitability for both constrained devices but also for server back-ends.
Finally, the overhead when adding confidentiality and authenticity for communication in an IoT device is evaluated. Here, modern lightweight protocols are utilized in multiple use-cases to give an overview of the overhead in terms of bytes, time, and energy.
|När:||2020-06-10 13:15 till 2020-06-10 13:15|
|Plats:||Online + E:1406, E-building, Ole Römers väg 3, LTH, Lund University|
Online presentation: From dimensional scaling to system-technology co-optimization
Title: From dimensional scaling to system-technology co-optimization
Speaker: Nadine Collaert, IMEC
Join through zoom: https://lu-se.zoom.us/j/65276229223
Abstract: With Moore?s law under pressure, a rethinking of what the semiconductor industry calls scaling will be needed. While it used to be all about scaling of the transistor, with still major industrial players looking at the next transistor beyond FinFET, these days there is more and more a push toward technology diversification, blending different technologies together to achieve benefits at the system level using System-Technology Co-Optimization (STCO), with 3D technologies taking a central stage.
Today a single CMOS technology often enables all functions in the system (SoC). However, emerging applications like machine learning, 5G, AR/VR... will require a variety of functionalities to be enabled (in memory computation, ultra-low power...) and might require different technologies to achieve this.
In this talk, we will give an overview of imec?s R&D activities in the area of logic, memory, 3D and RF, and the new trends towards enabling this vision of STCO.
Speaker CV: Dr. Nadine Collaert is program director at imec. She is currently responsible for the analog/RF program looking at heterogeneous integration of III-V/III-N devices with advanced CMOS to tackle the challenges of next generation mobile communication. Before that she was program director of the LOGIC Beyond Si program focused on the research on novel CMOS devices and new material-enabled device and system approaches to increase functionality. She has been involved in the theory, design, and technology of FinFET devices, emerging memories, transducers for biomedical applications and the integration and characterization of biocompatible materials.
|När:||2020-06-04 11:15 till 2020-06-04 11:15|
PhD Defence: III-V Nanowires for High-Speed Electronics (Fredrik Lindelöw)
Titel: III-V Nanowires for High-Speed Electronics
Author: Fredrik Lindelöw, Department of Electrical and Information Technology
Faculty opponent: Dr. Nadine Collaert, Belgien
When: 20 May at 9:15
Location: E:1406, E-building, Ole Römers väg 3, LTH, Lund University / Zoom: https://lu-se.zoom.us/j/66268490344
Thesis abstract: III-V compound materials have long been used in RF applications in high-electron-mobility-transistors (HEMTs) and bipolar-junction-transistors (BJTs). Now, III-V is also being viewed as a material candidate for replacing silicon in the n-channel in CMOS processes for increased drive currents and reduced power consumption in future nodes. Another alternative to increase the drive current is to use nanowire channels, where the increased electrostatic control can be utilized for scaling the gate length even further. In this thesis, we have characterized III-V nanowires with Hall-measurements to quantify the carrier concentration and optimize growth parameters. We have fabricated nanowire transistors for both digital and analog applications. Digital transistors made of a single nanowire show state-of-the art performance with low subthreshold slope and simultaneously high transconductance and high on-current. For RF applications, the nanowire technology faces several challenges, mainly due to its inherent higher parasitic capacitance since the filling factor is less than 1. To adapt the DC processing scheme to RF measurements, we have implemented T-gates, two-finger devices, 100 nanowires in parallel with tight pitch and we have developed novel spacer schemes with capacitances almost as low as recessed HEMT devices. These schemes consists of for instance modulation doped InP spacers as well as self-aligned air-spacers. To make the RF nanowire MOSFETs even more competitive, the transoncductance of RF devices needs to be optimized to match that of DC devices.
|När:||2020-05-20 09:15 till 2020-05-20 09:15|
|Plats:||E:1406, E-building, Ole Römers väg 3, LTH, Lund University / Zoom: https://lu-se.zoom.us/j/66268490344|