Elektro- och informationsteknik

Lunds Tekniska Högskola | Lunds universitet



Cadence Academic Network

The academic network was launched in 2007 by Cadence Europe. The aim was to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected European universities, research institutes, industry advisors and Cadence was established to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic systems. The department of Electrical- and Information Technology is member of the program since 2008. Cadence is associated industrial partner of the VINNOVA Industrial Excellence Center - System Design on Silicon (SOS).

The department of Electrical- and Information Technology is using Cadence tool extensively in both teaching and research. We are able to refer to dozen’s successful chip fabrications in various technologies, where Cadence tools were extensively used.

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Joachim Rodrigues (Ph. D)
Phone (+46) 46 222 48 68
Mobile (+46) 70 522 04 23

Projects at EIT where
Cadence tools were used

(Click to view the images in full size)

Four 32-bit Koggi stone adders were built to be operated and measured in Sub-Threshold regime. First adder is a simple and direct implementation, second adder is pipeline by a factor of 2, third adder is pipelined by 4 and the fourth implementation is done using only minimum sized gates with minimum load capacity e.g. X2 or X4 gates.

A Half band Filter Chain for decimation by a factor of 16 is built that has to be measured for Sub-Threshold operations for UPD project. The first filter is an unfolded by 4 architecture, second filter is unfolded by 2 architecture and the last two filter are original implementations.

The architecture is an auto-correlator for multiple Orthogonal Frequency Division Multiplexing systems. The received signal is quantized to only the sign-bit, which dramatically simplifies the frequency offset estimation. The architecture is designed specifically for for WLAN, LTE and DVB-H.

This single stage mixed-class power amplifier delivers a peak output power of +27dBm, which is implemented in a STM 65nm CMOS process.

The chip is taped out in ST 65nm 2010. It is a continuous time Delta-Sigma AD-converter clocked at 288MHz with 3-bit quantizer, Data-weighted averaging and 3rd order loop filter.

LNA and Mixer with improved linearity.

RF Front-end with LNA and mixer. Inductorless and ultra low power consumption of 175uW. Published at Norchip 2010.

RF front-end with LNA, mixer and frequency divider. Inductorless and ultra low power consumption. (Unpublished).

Pic 1: A 26-GHz LC-QVCO in 0.13-um CMOS (Infineon) (985µm x 985µm)


Pic 2a & 2b: A 20-GHz 130-nm CMOS Front-End using Baluns on Glass Carrier (CMOS:Infineon & Carrier:STMicroelectronics) (1435µm x 985µm & 5620µm x 4960µm)


Pic 3: A 25-GHz Differential LC-VCO in 90-nm CMOS (UMC) (600µm x 600µm)

Pic 4: A 24-GHz LC-QVCO in 130-nm CMOS using 4-bit Switched Tuning (Infineon) (985µm x 843µm)

Pic 5a & 5b: A 24 GHz VCO with 20 % tuning range in 130-nm CMOS using SOP Technology (CMOS:Infineon & Carrier:STMicroelectronics) (0.97mm2 & 5x5mm2)

Pic 6a & 6b: Two 24 GHz Receiver Front-ends in 130-nm CMOS using SOP Technology (CMOS:Infineon & Carrier:STMicroelectronics) (1.53mm2 & 5x5mm2)

Pic7: A 24-GHz Quadrature Receiver Front-end in 90-nm CMOS (UMC) (1075µm x 800µm)

Layout of an ultra low power analog decoder based on BCJR decoding algorithm. Digital I/O, timing circuitry, current comparators and D/As are also embedded to facilitate working with the analog computing core.

The chip is an implementation of an iterative decoder in a multicarrier faster-than-Nyquist (FTN) signaling receiver. It consists of a max-log-MAP decoder for a (7,5) convolutional code (outer decoder) and a symbol-by-symbol MAP decoder with Successive interference canceller (inner decoder) separated by interleaver/de-interleaver. Implemented in ST65nm CMOS the design takes up an area of 0.8mm^2.

A 5.4GHz Digitally Controlled Oscillator (DCO) with 3 tuning banks was implemented. It achieves -132dBc/Hz@3MHz for the 2.7GHz carrier, resulting in a FOM of 182dB. (2007)

An uneven-cell TDC based all digital phase-locked loop (ADPLL) achieves a measured phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. (2008)

A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented to achieve a 1st-order noise shaping. (2010)

(No description)

A ultra-wideband Low noise amplifier was implemented in a 90 nm CMOS process.

An injection locked VCO with digital phase control for beamforming was implemented in a 90 nm CMOS process.

PLL based 12GHz LO Generator with Digital Phase Control for beamforming was implemented in a 90 nm CMOS process.

A 24-GHz 90-nm CMOS Beamforming Receiver Front-End with Analog Baseband Phase Rotation


  Courses where we use Cadence tools
 Analogue IC-design  Digital IC- design
 Integrated A/D and D/A Converters  IC-project & Verification , digital
 Advanced AD/DA Converters  Advanced Analogue Design
  Research projects
 Wireless Communication for Ultra Portable Devices

 VINNOVA Industrial Excellence Center - System Design on Silicon





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