Godkända
BEAST on FPGA
Ali Roman ()
Start
2011-04-20
Presentation
2011-04-23 10:15
Plats:
Avslutat:
2012-04-26
Examensrapport:
Sammanfattning
Data decoders and decoding processes in modern communication systems are of significant importance for data reliability. The key challenge for a designer is to en- sure data reliability. With development of different channel coding schemes, variety of decoding algorithms are devised. The role of a hardware designer is to provide an efficient implementation of those algorithms for different hardware platforms. This thesis focuses on the hardware implementation of the BEAST (Bidirectional Efficient Algorithm for Searching Code trees) for decoding of block codes. A com- plete hardware is designed to implement the strategy of the BEAST[1][3]. The design is described using VHDL language. Besides describing the implementa- tion of the BEAST for FPGA (Field Programmable Gate Array) based platform, ASIC (Application Specific Integrated Circuits) synthesis of the design for an ASIC implementation is also discussed. Synthesis is a process of mapping the design com- ponents on basic logic gates. The results of the synthesis process can be used for implementation of the design on an ASIC platform. The architecture of the design is synthesized by using 130nm CMOS technology, resulting in area of 0.72469 mm2 and maximum clock frequency of 143 MHz. BER (Bit Error Rate) simulation is performed to verify the performance of the system for different SNR (Signal to Noise Ratio) values.
Handledare: Florian Hug (EIT)
Examinator: Joachim Rodrigues (EIT)