Godkända
Modeling and Implementation of All Digital PLL Frequency Synthesizer With Less Than 1KHz Frequency Resolution in 90-nm CMOS
Mohammed Abdullah Abdulaziz () och Muhammad Shakir ()
Start
2010-06-15
Presentation
2011-03-18 15:15
Plats:
E:2311
Avslutat:
2011-03-23
Examensrapport:
(Kontakta handledare)
Sammanfattning
Handledare: Ping Lu (EIT)
Examinator: Pietro Andreani (EIT)