Godkända
Fallstudie om Universal Verification Methodology(UVM) SystemC för RTL-verifiering
Kevin Skaria Chacko (2017)
Start
2018-11-05
Presentation
2019-05-24 11:15
Plats:
E:2349
Avslutat:
2019-08-23
Examensrapport:
Sammanfattning
Verification of ASIC’s are important nowadays especially in terms of production costs, time to market and the sustainability of products. As the Moore’s Law is in motion, verification gets large and more complex. The need for verification engineers working in an ASIC/IC project has surpassed the design engineers since a few years for the same reason. Industries are trying to find faster and efficient methods to verify more complex designs in order to reach the market first. The most popular ASIC verification method is the functional verification. The traditional Verilog or VHDL test bench usually cannot be scaled up to ensure reliable verification of complex designs. Verification is completed only when every item on the design has been verified to a level of acceptance, where these levels have been decided in advance and reviewed iteratively during the project. Universal Verification Methodology or UVM is such a methodology agreed upon by the EDA vendor industries. It enables to create modular, scalable, configurable and reusable test benches. The class library brings automation to the standard System Verilog language by introducing sequences and data automation features. As there is a strong need for system-level verification for all embedded systems nowadays, System C based UVM is introduced which is faster to execute in simulators even though they have some limitations compared to System Verilog based UVM.
Handledare: Liang Liu (EIT)
Examinator: Erik Larsson (EIT)