Godkända
Design of a Pacman with Debug Logic
Dinesh Kothamasu (2013)
Start
2017-03-17
Presentation
2018-03-22
Plats:
Avslutat:
2018-04-06
Examensrapport:
Sammanfattning
Ineda Systems has developed a customized processor with extremely low power consumption. This Target Processor is in need of a debug feature. This Master thesis deals with the designing of a Debugger so that we can debug the Processor from the external world. This Master thesis includes with the implementation of a debug logic for the Target Processor, a Jtag to AHB Access Port, a Debugger and a Assembly Compiler. The Processor acts as a slave to this AHB Access Port . The interface between the Compiler and the Debugger is through USB while the interface between the Debugger and the FPGA board is through Jtag. However, if time permits, the Assembly Compiler can be upgraded to the GCC C Compiler which can also be considered but will not be the primary focus of this thesis. The thesis should include end to end solution starting from Target Processor to PC.
Handledare: Johan Wernehag (EIT)
Examinator: Pietro Andreani (EIT)