Laborationer
There are scheduled six laboratory lessons (each four hours) in the course. The first two in period one (week 3 and 6) and the remaining four in period two (week 2, 3, 4, and 5). The laboratory is located on the fourth floor in the northen part of the E-building (E:4116-4119).
Connected to each lesson there is a number of problems. Since the work during the lessons are based on these problems, it is important that they are solved before the lesson starts. The work with the problems is, in some cases, quite extensive with 4-6 hours for each lesson. So, start in good time before the lesson.
Note that if you have not solved the majority of the problems, you will not be allowed to do the lab.
You sign up to the lab following the "sign up" link.
For any questions regarding the laboratory lessons contact Andreas Johansson.
Lab 4
During the 4:th lab you are going to develop a stop watch using VHDL. You will be writing some VHDL code, simulate the design and finally test it on a Nexys4 FPGA development board. To be well prepared, download the lab files below and have a look at them before the lab.
To simulate the behaviour of your design a simulation tool called Questa Sim will be used during the lab. A free student version (called Model Sim) is available from Mentor Graphics webpage, which you can install on your computer if you want to test some code at home.
If you have written some VHDL code at home and want to bring it to the lab use a USB stick, Dropbox, Googledrive etc.
Lab 5
För laboration 5 kommer det att ges handledning under två tillfällen (laboration 5 & 6 på anmälningssidan). Ni kommer även att ha tillträde till labblokalerna, E:4116 & E:4118, på övriga tider då där inte bedrivs någon undervisning. Ni kommer in i lokalerna med ert LU-kort.
Det finns inget delmål som ni måste klara av under labbpass 5. Ni redovisar när ni är klara med hela laborationen, dock senast på labbpass 6!
För att underlätta felsökning av er cpu kan ni använda testbädden cpu_tb nedan. Testbädden simulerar exekveringen av en sekvens instruktioner som är specificerad i filen cpu_tb_info.txt. Under simuleringen kommer testbädden att undersöka er CPUs utsignaler. Skulle dessa avvika från förväntade värden visas ett felmeddelande i Questa Sims transcript-fönster.