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Lunds Tekniska Högskola | Lunds universitet

ETI220 Integrerade A/D och D/A omvandlare

FAQ

2011/2012


Assignment 1, Homework problem 1.8.
?
I have no idea how to solve this...
! Half the quantization noise power equals 0.5 * Delta^2 / 12 should equal the jitter power (Ain^2)/2 * win^2 * sig_j^2 where Delta is the quantization step voltage ( Delta = 2Ain / (2^R)), win is the input radian frequency, Ain is the maximum signal amplitude, and sig_j is the standard deviation of the clock jitter. Set the two powers equal and solve for sig_j which should be on the order of 1 ps.

Assignment 1, 1.5.
? How do I add a random noise with rms value 0.56382 mV to a signal in MATLAB?
! Try, this:

> t = (0:1/100:1); f=1;           % Time vector
> sig = sin(2*pi*f*t);              % Signal vector
> noise = randn(size(sig))*0.56382e-3;  % Noise vector with same size as sig
> sig_n = sig + noise;                % Signal plus noise 

Assignment 1, 1.5.
? Why do I not see any difference between the FFT with averaging and the one without averaging?
! You still use fs=80 MHz, so you are only looking at FFT leakage and not at the noise you added. Change back to fs=81.92 MHz.

Assignment 1, 1.7.
?
How to create a 3rd order harmonic tone at 3*fin?
! One way is to set k3 equal to 0.01 in the sampling.m file.

Assignment 1, 1.8.
?
I cannot find the 'snoise' parameter in sampling.m, is there something wrong?
! Yes, snoise is an old parameter that has been removed. Now it is enough to specify only 'Cs'.

Assignment 1, 1.10.
? I am confused about what signal frequency to use, 100 MHz or fin = 3277/8192*fs?
! Use fin = 3277/8192*fs to approximate 100 MHz, to avoid FFT leakage problems.

Assignment 2, part 2.
? What syntax can I use to assign a logic variable to an output voltage?

!
Use the transition command as shown in seminar slide 41. Check the Verilog-A Language Reference for details.

Assignment 2, part 3.
? What syntax can I use to measure the time between two zero crossings?
! To detect a zero crossing, use the @cross statement. To get the time of the zero crossing use the Verilog-A environment parameter function $abstime or $realtime. If you have any doubts on how to do this, use your problem solving skills and take a look in the Verilog-A Language Reference to get more information.

Assignment 2, part 3.
? What syntax can I use to open, write and close a file in Verilog-A?
! To open a file (preferably inside the @(initial_step)) use $fopen. To write a string to a file, use $fstrobe. To close the file (preferably inside the @(final_step)), use $fclose. If you have any doubts on how to do this, use your problem solving skills and take a look in the Verilog-A Language Reference to get more information.

Assignment 2, part 3.
? What syntax can I use to write variables to a file?
! Try the $fstrobe like this:
$fstrobe(outfile, "%-.10g \t %-.10g", $abstime, foutvar)
This will write the simulator time $abstime and the variable foutvar to the file opened in outfile. The %-.10g statement will give 10 digits of precision output format. \t is the tab operator. For a complete list of the output formats available in Verilog-A, please take a look in the Verilog-A Language Reference.

Assignment 2, part 5.
? What syntax can I use to access the tabulated data on the text file?
! Use the $table_model command as explained on seminar slide 43.  If you have any doubts on how to do this, take a look in the Verilog-A Language Reference to get more information.

Assignment 3, getting started
? I cannot find the SpectreVerilogLab library in the Library Manager, what to do?
! Add the library by clicking Edit -> Library Path... in the Library Manager and then adding the SpectreVerilog library to your list of libraries. After editing, the entry should turn to blue color and you can save the settings by clicking File -> Save As... in the Library Path Editor. Save the settings to the default cds.lib so that they will be automatically loaded the next time you start Cadence.

Assignment 3, getting started
? I cannot open some of the files with write permission, only read. What to do?
! You have to remove all Cadence lock files. You can do that by finding the cellview files in the file system (using a terminal window) and then type rm *.cdslck. Now you should be able to open the cellviews with write permission.

Assignment 3, getting started
? I have removed all .cdslck files but can still not edit the schematics.
! Try clicking Edit -> Make Editable in your schematic window.

Assignment 3, glitches
? Both the flash and pipelined ADC have glitches on the output, is this ok or did I do something wrong?
! The glitches are due to the infinitely fast, ideal, DAC converting of the ADC output that has a finite rise/fall time.  They are ok, the important thing is the value of the signal at the constant levels between the glitches.

Assignment 3, Flash ADC.
? In ramp simulation, I see that the LSB of the flash ADC is constant mostly. Why?
! The settings for the input signal ramp are too short in the files you have been given. Change to  (t1=0,V1=-484.4m), (t2=100n,V2=-484.4m), (t3=3.3u,V3=515.6m), (t4=3.4u,V4515.6m), in order to sample once for every output level of the 5 bit ADC.

Assignment 3, Flash ADC.
? I have changed the input ramp, but my output is non-monotonic, even though I have am running an ideal simulation. Why?
! Make sure that the offset of all comparators are identical to 0. There might be one or two comparators with non-zero offset in the files you were given. Sorry.

Assignment 3, Flash ADC.
? I found that the output of the encoder of the flash ADC is in the range of 0 to 3.3 V, is this ok and what standard cells should I use?
! Use the standard cells in the CORELIB library, they have a supply voltage of 3.3V, so it should be ok.

Assignment 3, Flash ADC.
?
When I simulate the config view of the Tb, Cadence gives a warning regarding $digital in the "inherited view list" saying that it can't find it. What is this about?
! The $digital is a constant that is used in the Hierarchy Editor (HE) instead of the complete view list to simplify the settings. It can be defined by clicking Edit -> Constants in the HE and then adding the desired views to the $digital constant.

Assignment 3, Pipeline ADC.
? The pipeline ADC simulation is not starting, the error message complains about the SampleToFile block.
! You have to edit the properties (by clicking q) of the SampleToFile block, so that the file where data shall be saved is a file in your own home directory.

Assignment 3, Pipeline ADC.
? I still have problems using the INLDNL.m function. What is the problem?

!
You should delete the initial values in the output data file, so that you have exactly ten identical values at the beginning of that text file.

Assignment 3.9, Pipeline ADC.
?
I have problems setting the path according to the lab manual! What have I done wrong?
! Nothing. This is an error in the text. It is no longer possible to save simulation data locally, so just set the path to the default. If you want to save disk space, don't save all nodes in the circuit.

Assignment 3, Pipeline ADC.
? I have problems getting a good DFT in Cadence.

When simulating with a sine input, try using fsig=x/N*fs, where x is a prime number, N is 1024 and fs is 2 MHz. Simulate for 520 us. Setup the DFT from for example 3 us to 515us, with 1024 data points. Now the DFT should look better.