Laboratory Lessons
Important Notes:
- TA will be available ONLY in 50% of each lab session.
- Note that all TAs can help you on the labs. But, ONLY the corresponding TA can approve you in the labs as follows:
- Lab 1: Steffen Malkowsky (SM)
- Lab 2: Masoud Nouripayam (MN)
- Lab 3: Mojtaba Mahdavi (MM)
- Lab 4,5: Jesús Rodríguez (JR)
- So, please look at the TA schedule to see when the corresponding TA is available in the lab.
- Checklist:
- Please read the checklist file for each lab and prepare the requirements before coming to the lab.
Assignment 1: Sequence Detector (Testfiles Sequence) (updated: 11/09 16.15, the ones missing send an email with your group to Steffen)
Assignment 2: Keyboard Controller (Presentation, Lab_Manual, VHDLfiles)
Assignment 3: ALU (Presentation, Lab_Manual, VHDL Files, Modulo3)
Assignment 4 and 5: Two paths:
- Calculator with memory and VGA display. (Lab Manual 4, 5, Presentation, Matlab Files, CORDIC Intro, Report Template)
- Machine learning: CNN (presentation, project files and instruction manual)
NOTE: LAB4 and LAB5
- When using the reference design, the coe file for the ROM needs to be pointed to the correct location before synthesis. The location of the coe file is "YOUR_PJT\VGA_REF_DESIGN\VGA_REF_DESIGN.srcs\sources_1\imports\vhdl\ip_core\welcome_480x120.coe"
- Please use:
- use ieee.std_logic_arith.all;
- use ieee.std_logic_unsigned.all;
instead of IEEE.NUMERIC_STD.ALL to maintain compatibility with the VGA reference design
- A few slides on Questasim are here.
- A few slides on using Xilinx Vivado are here.
- An example project for using Xilinx IP generators and ILA can be downloaded here.
NOTE: If you have logged in the first time using your account, you might have problems accessing licences. Log off and log back in and it should fix the problem.
NOTE: Create your Vivado projects inside C:\Users\login-id\Program\YOUR_DIRECTORY where YOUR_DIRECTORY is the directory where you save all your work