Kursprogram
Lectures
Use HP book 5th Edition (6th Edition is avaliable now)
Detailed schedule can be found here:
Schedule (the schedule is preliminary, can subject to changes during the course):
- 2018-11-06: Performance, Quantitative principles; HP Ch. 1 (slides)
- 2018-11-08: Instruction set architectures, ISA; HP Ch. 1.3, App. A (slides);
- 2018-11-13: Pipelining I; HP App. C.1-C.5 (slides)
- 2018-11-15: Pipelining II; HP App. C.6-C.7, C.2, Ch. 3.1-3.2, 3.9 (slides)
- 2018-11-20: Pipelining III; HP Ch. 3.4-3.8,3.10-3.11 (slides)
- 2018-11-22: Memory systems, cache I; HP Ch 2.1, App. B.1-B.2 (slides)
- 2018-11-27: Exercise I
- 2018-11-29: No Lecture
- 2018-12-04: Memory systems, cache II; HP Ch. 2.2-2.3, App. B.3 (slides)
- 2018-12-06: Memory systems, virtual memory; HP App B.4, Ch. 2.5-2.6 (slides)
- 2018-12-11: Invited Lecture Ericsson, AI processor (slides)
- 2018-12-13: Multi-core HP App D, Ch. 5.1-5.2 (slides);
- 2018-12-18: Exercise II
- 2018-12-20: No Lecture
A good overview of Computer Architecture: Jason Patterson, "Modern Microprocessors - A 90 Minute Guide"
Article: GPU vs. CPU Computing"
, "Laboratories
There are 4 laboratories
Lab assignments/manual.
You need to sign up for the labs via the 'Sign up' page in the menu to the left! (Rooms E:4115, E:4118, E:4119)
- (Week 46) Pipelined processors.
- (Week 47) Advanced pipelining.
- (Week 48) Cache memory.
- (Week 49) Advanced cache, cache coherence.
Assessment
Examination through approved labs followed by a successful written examination