ABI
| Applications binary interface
|
ADSP
| Advanced digital signal processing
|
AGP
| Accelerated graphics port
|
AI
| Artificial intelligence
|
AIX
| Advanced Interactive Executive, IBM's UNIX
|
ALC
| Assembly language code
|
ALU
| Arithmetic logic unit
|
AMD
| Advanced Micro Device
|
ANSI
| American National Standards Institute
|
API
| Application programming interface
|
ARB
| 1. Address resolution buffer
|
| 2. Address reorder buffer
|
ARM
| Advanced RISC Machines
|
ARPA
| Advanced Research Projects Agency
|
AS
| Activity store
|
ASCII
| American Standard Code for Information Interchange
|
ASIC
| Application specific integrated chip
|
async
| Asynchronous
|
ATM
| Asynchronous transfer mode
|
ATR
| Automatic target recognition
|
CAD
| Computer-aided design
|
CAE
| Computer-aided engineering
|
CalTech
| California Institute of Technology
|
CAM
| 1. Computer-aided manufacturing
|
| 2. Content addressable memory
|
CAN
| Campus area network
|
CAP
| Complexity-adaptive processor
|
CASE
| Computer aided software environment
|
CCITT
| Comité consultatif internationale de télégraphique et téléphonique
|
CC-NUMA
| Cache-coherent non-uniform memory access
|
CCR
| Condition code register
|
CDB
| Condition data bus
|
CDRAM
| Cache dynamic random access memory
|
CD-ROM
| Compact disk, read-only memory
|
CFG
| Control flow graph
|
CISC
| Complex instruction set computer
|
CMOS
| Complementary metal oxide semiconductor
|
CMP
| (single)-chip multiprocessor
|
CN
| Communication network
|
cold
| Computer output to laser-disk
|
comm
| Communications
|
CP
| Computational processor
|
CPGA
| Ceramic pin grid array
|
CPI
| Clock cycles per instruction
|
CPU
| Central processing unit
|
CQ
| Continutation queue
|
CQFP
| Ceramic quad flat pack
|
CRCW
| Concurrent read concurrent write
|
CSB
| Context switch buffer
|
CSMA/CD
| Carrier sense multiple access/collision detection
|
CWP
| 1. Current window pointer
|
| 2. Current word pointer
|
DARPA
| Defense Advanced Research Projects Agency
|
DASD
| Direct-access storage device
|
datacomm
| Data communications
|
DBMS
| Database management system
|
D-cache
| Data cache
|
DCE
| Distributed computing environment
|
DCM
| Data control memory
|
DEA
| Direct external access
|
DEC
| Digital Equipment Corporation
|
demux
| Demultiplex
|
DG
| Data General Corporation
|
DISC
| Dynamic instruction set computer
|
DMA
| Direct memory access
|
DMEM
| Data memory
|
DOD
| Department of Defense (USA)
|
DOE
| Department of Energy
|
DOS
| Disk operating system
|
DRAM
| Dynamic random-access memory
|
DSM
| Distributed shared-memory multiprocessor
|
DSP
| Digital signal processing
|
DSS
| Decision support system
|
DU
| Decode unit
|
DVD
| Digital versatile disc
|
ECC
| Error correcting code
|
ECL
| Emitter coupled logic
|
ECU
| External cache unit
|
EDO
| Extended data output
|
EDVAC
| Electronic discrete variable automatic computer
|
EEPROM
| Electrically erasable programmable read-only memory
|
EIA
| Electronic Industries Association
|
EISA
| Extended industry standard bus (32-bit)
|
E-mail
| Electronic mail
|
EMI
| Electromagnetic interference
|
EMIF
| External memory interface
|
EPIC
| Explicitly parallel instruction computing
|
EPROM
| Erasable programmable read only memory
|
ESDI
| Enhanced small device interface
|
ETS
| Explicit token store
|
EX
| Execution (pipeline stage)
|
EU
| Execution unit
|
IA-32
| Intel 32-bit architecture
|
IA-64
| Intel 64-bit architecture
|
IBM
| International Business Machines
|
IBU
| Input buffer unit
|
IC
| Integrated circuit
|
I-cache
| Instruction cache
|
ICM
| Instruction control memory
|
ID
| Instruction decode (pipeline stage)
|
IDT
| Integrated Device Technology
|
IEEE
| Institute of Electrical and Electronics Engineers
|
IEF
| Information Engineering Faculty
|
IEU
| Integer execution unit
|
IF
| Instruction fetch (pipeline stage)
|
IFU
| Instruction fetch unit
|
IGES
| Initial Graphics Exchange Standard
|
ILP
| Instruction-level parallelism
|
IM
| Instruction memory
|
iMRC
| Intel's mesh router component (chip)
|
Intel SSD
| Intel Supercomputer Systems Division
|
I/O
| input-output
|
IOC
| Input/output cache
|
IOP
| Input/output processor
|
IPC
| Instruction per clock cycle
|
IPD
| Interactive parallel debugger
|
IPI
| Intelligent peripheral interface
|
IQ
| Instruction queue
|
IRAM
| Intellligent random access memory
|
IRB
| Instruction reorder buffer
|
IS
| Issue (pipeline stage)
|
ISA
| 1. Instruction set architecture
|
| 2. Industry standard architecture (16-bit bus)
|
ISDN
| Integrated services digital network
|
ISO
| International Standards Organization
|
ISSE
| Internet streaming SIMD extension
|
ISU
| Instruction store unit
|
I-tlb
| Instruction translation lookaside buffer
|
IU
| 1. Integer unit
|
| 2. Issue unit
|
M
| Mega (times 106)
|
MAN
| Metropolitan area network
|
MAX
| 1. Multimedia acceleration extension
|
| 2. Maximum
|
MB
| Megabyte
|
M-bus
| Memory bus architecture from Sun Microsystems
|
MCA
| Microchannel architecture (32-bit bus)
|
MCA-E
| Microchannel architecture-extended (64-bit bus)
|
McBSP
| Multi-channel buffered serial port
|
MCU
| Memory control unit
|
MDC
| Miss distance counter
|
MDCE
| Multidimensional directed cycles ensemble
|
MDMX
| MIPS digital media extension
|
MDP
| Message driven processor
|
MEM
| Memory access (pipeline stage)
|
MESI
| Modified, exclusive, shared, invalid
|
MFLOPS
| Mega (106) floating point operations per second
|
MHz
| Megahertz
|
MIMD
| Multiple-instructions, multiple-data
|
MIPS
| 1. Microprocessor without interlocking pipeline stages
|
| 2. Millions of instructions per second
|
MIT
| Massachussetts Institute of Technology
|
MMU
| Memory Management Unit
|
MMX
| Matrix multiplication extensions
|
MoM
| Map-oriented machine
|
MP
| Master processor
|
MPEG
| Motion Picture Experts Group
|
MPI
| Message-passing interface
|
MU
| 1. Matching unit
|
| 2. Memory unit
|
MUX
| Multiplexer
|
MVI
| Motion video instruction
|
MVP
| Multimedia video processor
|
PA
| Precision architecture
|
PA-RISC
| Precision architecture RISC
|
PBHT
| Per-address branch history table
|
PC
| Program Counter
|
PCI
| Peripheral component interconnect
|
PDP
| Programmed data processor
|
PDU
| Prefetch and dispatch unit
|
PE
| Processing element
|
PGP
| Pretty good privacy (encryption)
|
PHT
| Pattern history table
|
PIM
| Processor-in-memory
|
PISA
| Pixel-oriented system for image analysis
|
PM
| Program memory
|
POLU
| Problem-oriented logic unit
|
POWER
| Performance optimization with enhanced RISC
|
PP
| Parallel processor
|
PRISM
| Parallel reduced instruction set multiprocessor-Apollo Computer
|
PRAM
| Parallel random access machine
|
P-RISC
| Parallel reduced instruction set computer
|
PS
| Program store
|
PSE
| Parallel software environment
|
PSR
| Processor state (status) register
|
PTREQ
| Packet transfer request
|
PU
| Processing unit
|
PVM
| Parallel virtual machine
|
SCI
| Scalable component interconnect (IEEE 1596-1992 standard)
|
SCO
| Santa Cruz Operation, variant of Unix
|
SCSI
| Small computer system interface
|
SDI
| Scalable delay-intensive
|
SDRAM
| Synchronized dynamic random access memory
|
SFU
| Special-function unit
|
SGI
| Silicon Graphics International
|
SHARC
| SuperHarvard Architecture, by Analog Devices
|
SIA
| Semiconductor Industry Association
|
SIMD
| single-instruction, multiple data
|
SIMM
| Single inline memory module
|
SISD
| Single instruction, single data
|
SLDRAM
| Synchronous-line dynamic random access memory
|
SLRAM
| Synchronous-line random access memory
|
SMEM
| Switch with instruction memory
|
SMM
| System management mode, used for power management
|
SMP
| symmetric multiprocessor
|
SMT
| simultaneous multithreading
|
SNA
| Systems network architecture
|
SONET
| Synchronous optical network standard
|
SPARC
| Scalable processor architecture
|
SPEC
| System Performance and Evaluation Cooperative
|
SPMD
| Single-program, multiple-data
|
SPSD
| Single-program, single-dataread-only memory
|
SQL
| Structured query language
|
SRAM
| Static random-access memory
|
SSW
| Stream status word
|
SU
| 1. Send unit
|
| 2. Switching unit
|
| 3. Synchronization unit
|
sync
| Synchronous; synchronized
|