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      Acronyms


A B C D E F G H I J K L M N O P Q R S T U V W X Y Z µ 0-9


A

ABI Applications binary interface
ADSP Advanced digital signal processing
AGP Accelerated graphics port
AI Artificial intelligence
AIX Advanced Interactive Executive, IBM's UNIX
ALC Assembly language code
ALU Arithmetic logic unit
AMD Advanced Micro Device
ANSI American National Standards Institute
API Application programming interface
ARB 1. Address resolution buffer
2. Address reorder buffer
ARM Advanced RISC Machines
ARPA Advanced Research Projects Agency
AS Activity store
ASCII American Standard Code for Information Interchange
ASIC Application specific integrated chip
async Asynchronous
ATM Asynchronous transfer mode
ATR Automatic target recognition

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B

BCD Binary coded decimal
BEAR Bus error address register (Intel i860)
BER Bit error rate
BERT Branch effect reduction technique
BHR Branch history register
BHT Branch history table
B-ISDN Binary integrated services digital network
bpi Bits per inch
BSD Berkeley Systems Distribution (Unix)
BTAC Branch target address cache
BTB Branch target buffer
BTC Branch target cache

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C

CAD Computer-aided design
CAE Computer-aided engineering
CalTech California Institute of Technology
CAM 1. Computer-aided manufacturing
2. Content addressable memory
CAN Campus area network
CAP Complexity-adaptive processor
CASE Computer aided software environment
CCITT Comité consultatif internationale de télégraphique et téléphonique
CC-NUMA Cache-coherent non-uniform memory access
CCR Condition code register
CDB Condition data bus
CDRAM Cache dynamic random access memory
CD-ROM Compact disk, read-only memory
CFG Control flow graph
CISC Complex instruction set computer
CMOS Complementary metal oxide semiconductor
CMP (single)-chip multiprocessor
CN Communication network
cold Computer output to laser-disk
comm Communications
CP Computational processor
CPGA Ceramic pin grid array
CPI Clock cycles per instruction
CPU Central processing unit
CQ Continutation queue
CQFP Ceramic quad flat pack
CRCW Concurrent read concurrent write
CSB Context switch buffer
CSMA/CD Carrier sense multiple access/collision detection
CWP 1. Current window pointer
2. Current word pointer

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D

DARPA Defense Advanced Research Projects Agency
DASD Direct-access storage device
datacomm Data communications
DBMS Database management system
D-cache Data cache
DCE Distributed computing environment
DCM Data control memory
DEA Direct external access
DEC Digital Equipment Corporation
demux Demultiplex
DG Data General Corporation
DISC Dynamic instruction set computer
DMA Direct memory access
DMEM Data memory
DOD Department of Defense (USA)
DOE Department of Energy
DOS Disk operating system
DRAM Dynamic random-access memory
DSM Distributed shared-memory multiprocessor
DSP Digital signal processing
DSS Decision support system
DU Decode unit
DVD Digital versatile disc

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E

ECC Error correcting code
ECL Emitter coupled logic
ECU External cache unit
EDO Extended data output
EDVAC Electronic discrete variable automatic computer
EEPROM Electrically erasable programmable read-only memory
EIA Electronic Industries Association
EISA Extended industry standard bus (32-bit)
E-mail Electronic mail
EMI Electromagnetic interference
EMIF External memory interface
EPIC Explicitly parallel instruction computing
EPROM Erasable programmable read only memory
ESDI Enhanced small device interface
ETS Explicit token store
EX Execution (pipeline stage)
EU Execution unit

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F

FDDI Fibre distributed data interface
FEU Fetching unit
FIFO First-in, first-out
FIPS Federal Information Processing Standards
FLOPS Floating-point operations per second
FM Frame memory
FMAC Floating-point multiply accumulate
FMU Fetch/matching unit
FPAA Field programmable ALU array
FPGA Field programmable gate array
FPU Floating-point Unit
FTU Form token unit
FU 1. Functional unit
2. Fetch unit
FUD Fear, uncertainty, doubt

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G

G Giga (times 109)
GAG Generic address generator
GB Gigabyte
GFLOPS Giga (109) floating point operations per second
GIPS Giga (109) operations per second
GM Global memory
GOSIP Government Open Systems Interconnection Profile
GRU Graphics unit
GUI Graphical user interface

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H

HDTV High-definition television
HIPPI High performance parallel interface
HLL High-level language
HP Hewlett-Packard
HPI Host-port interface
Hz Hertz, cycles per second

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I

IA-32 Intel 32-bit architecture
IA-64 Intel 64-bit architecture
IBM International Business Machines
IBU Input buffer unit
IC Integrated circuit
I-cache Instruction cache
ICM Instruction control memory
ID Instruction decode (pipeline stage)
IDT Integrated Device Technology
IEEE Institute of Electrical and Electronics Engineers
IEF Information Engineering Faculty
IEU Integer execution unit
IF Instruction fetch (pipeline stage)
IFU Instruction fetch unit
IGES Initial Graphics Exchange Standard
ILP Instruction-level parallelism
IM Instruction memory
iMRC Intel's mesh router component (chip)
Intel SSD Intel Supercomputer Systems Division
I/O input-output
IOC Input/output cache
IOP Input/output processor
IPC Instruction per clock cycle
IPD Interactive parallel debugger
IPI Intelligent peripheral interface
IQ Instruction queue
IRAM Intellligent random access memory
IRB Instruction reorder buffer
IS Issue (pipeline stage)
ISA 1. Instruction set architecture
2. Industry standard architecture (16-bit bus)
ISDN Integrated services digital network
ISO International Standards Organization
ISSE Internet streaming SIMD extension
ISU Instruction store unit
I-tlb Instruction translation lookaside buffer
IU 1. Integer unit
2. Issue unit

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J

JPEG Joint Photographic Experts Group
JTAG Joint Test Action Group (IEEE)
JVM Java virtual machine

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K

K Kilo (times 103)
kB Kilobyte
KNI Katmai new instructions
KSR Kendall Square Research (MPP vendor)

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L

L1 Level-one (primary) cache
L2 Level-two (secondary) cache
L3 Level-three (tertiary) cache
LAN Local area network
LCC Latch control unit
LIFO Last-in, first-out
LIPS Logical inferences per second
LIW Long instruction word
LOC Library of Congress
LRU Least recently used
LSB Least significant bit or byte
LSU Load and store unit

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M

M Mega (times 106)
MAN Metropolitan area network
MAX 1. Multimedia acceleration extension
2. Maximum
MB Megabyte
M-bus Memory bus architecture from Sun Microsystems
MCA Microchannel architecture (32-bit bus)
MCA-E Microchannel architecture-extended (64-bit bus)
McBSP Multi-channel buffered serial port
MCU Memory control unit
MDC Miss distance counter
MDCE Multidimensional directed cycles ensemble
MDMX MIPS digital media extension
MDP Message driven processor
MEM Memory access (pipeline stage)
MESI Modified, exclusive, shared, invalid
MFLOPS Mega (106) floating point operations per second
MHz Megahertz
MIMD Multiple-instructions, multiple-data
MIPS 1. Microprocessor without interlocking pipeline stages
2. Millions of instructions per second
MIT Massachussetts Institute of Technology
MMU Memory Management Unit
MMX Matrix multiplication extensions
MoM Map-oriented machine
MP Master processor
MPEG Motion Picture Experts Group
MPI Message-passing interface
MU 1. Matching unit
2. Memory unit
MUX Multiplexer
MVI Motion video instruction
MVP Multimedia video processor

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N

n Nano (times 10-9)
NCC Non-cache coherent
nm Nanometer
NOW Network of workstations
NS National Semiconductiors
NUMA Non-uniform memory access

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O

OFU Operand fetch unit
OLTP Online transaction processing
OSU Operand store unit
OU Operation unit

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P

PA Precision architecture
PA-RISC Precision architecture RISC
PBHT Per-address branch history table
PC Program Counter
PCI Peripheral component interconnect
PDP Programmed data processor
PDU Prefetch and dispatch unit
PE Processing element
PGP Pretty good privacy (encryption)
PHT Pattern history table
PIM Processor-in-memory
PISA Pixel-oriented system for image analysis
PM Program memory
POLU Problem-oriented logic unit
POWER Performance optimization with enhanced RISC
PP Parallel processor
PRISM Parallel reduced instruction set multiprocessor-Apollo Computer
PRAM Parallel random access machine
P-RISC Parallel reduced instruction set computer
PS Program store
PSE Parallel software environment
PSR Processor state (status) register
PTREQ Packet transfer request
PU Processing unit
PVM Parallel virtual machine

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Q

QDI Quasi delay insensitive
QFP Quad flat pack
QPFP Quad plastic flat pack

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R

RAID Redundant array of inexpensive disks
rALU Reconfigurable arithmetic logic unit
RAM Random-access memory
RAS Return address stack
RAW Read after write
RC Reconfigurable cell
RCA Radio Corporation of America
rDPA Reconfigurable data path architecture
RGB Red-green-blue
RICA Reduced interprocessor-communication architecture
RISC reduced instruction set computer
RO Read operand (pipeline stage)
ROM Read-only memory
ROMP Research Office Products Division microprocessor
RS Reservation station
RTOS Real-time operating system
RU 1. Receive unit
2. Retire unit

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S

SCI Scalable component interconnect (IEEE 1596-1992 standard)
SCO Santa Cruz Operation, variant of Unix
SCSI Small computer system interface
SDI Scalable delay-intensive
SDRAM Synchronized dynamic random access memory
SFU Special-function unit
SGI Silicon Graphics International
SHARC SuperHarvard Architecture, by Analog Devices
SIA Semiconductor Industry Association
SIMD single-instruction, multiple data
SIMM Single inline memory module
SISD Single instruction, single data
SLDRAM Synchronous-line dynamic random access memory
SLRAM Synchronous-line random access memory
SMEM Switch with instruction memory
SMM System management mode, used for power management
SMP symmetric multiprocessor
SMT simultaneous multithreading
SNA Systems network architecture
SONET Synchronous optical network standard
SPARC Scalable processor architecture
SPEC System Performance and Evaluation Cooperative
SPMD Single-program, multiple-data
SPSD Single-program, single-dataread-only memory
SQL Structured query language
SRAM Static random-access memory
SSW Stream status word
SU 1. Send unit
2. Switching unit
3. Synchronization unit
sync Synchronous; synchronized

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T

T Tera (times 1012)
TAP Test access port
TB Terabyte
TCP/IP Transmission control protocol/internet protocol
TFLOPS Tera (1012) floating-point operations per second
TI Texas Instruments
TIFF Tag image file format
TIPS Tera (1012)operations per second
TLB translation lookaside buffer
TMC Thinking Machines Corporation
TME Threaded multipath execution
TPC Transaction processing council
tps Transactions per second
TQ Token queue
TQFP Thin quad flat pack
TTL Transistor-transistor logic

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U

UART Universal Asynchronous Receiver Transmitted
UMA Uniform memory access
USART Universal synchronous/asynchronous receiver transmitter
USL Unix Systems Lab
UU Update unit
UV-PROM Ultraviolet(erasable) programmable read-only memory

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V

VAX Virtual Architecture Extended
VC Video controller
VDRAM Video random-access memory
VESA Video Electronics Standards Association (bus)
VHDL Very high-speed integrated circuit hardware description language
VIS Visual instruction set
VLIW Very large instruction word
VLSI Very large-scale integrated
VRAM Video random-access memory
VUP Vax unit of performance
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W

W 1. Word
2. Watt
WABI Windows application binary interface (under Unix)
WAN Wide area network
WAR Write after read
WAW Write after write
WB Write-back (pipeline stage)
WIMP Window, icon, menu, pointer
WMU Wait-match unit
WORM Write once, read many (or mostly)
WWW World wide web (of the Internet)

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X


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Y


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Z


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µ

µ Micro (times 10-6)
µm Micron

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0-9

3GL Third-generation (computer) language, COBOL, FORTRAN, C
4GL Fourth-generation (computer) language, nonprocedural
5GL Fifth-generation (computer) language-usually object oriented
80x86 CISC family from Intel, 8086, 80286, 80386, 80486, etc...

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