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DTSTAMP:20261015T165944Z
SUMMARY:Exjobbspresentation: Thermal-Aware Floorplan techniques for ASICs
DESCRIPTION:Kontakt: susanna.lonnqvist@eit.lth.se\n\nExjobbet genomfördes 
 hos Ericsson med Ali Zaher som handledare\, Victor Åberg som akademisk ha
 ndledare och Pietro Andreani som examinator.As transistors get smaller and
  smaller\, the power density of an integrated circuit increases and thus t
 he temperature increases. In an application specific integrated circuit (A
 SIC) the layout is tailor-made for each design\, so the thermal signature 
 of each component can be taken into account during the floorplanning proce
 ss. Although approaches for thermal aware floorplanning exists\, they aren
 ’t generalizable to new floorplans and can’t handle hierarchical struc
 tures adequately. In this thesis we present a method to do thermalaware co
 mpact floorplanning that is also generalizable through the use of reinforc
 ement learning. We present a novel way to do hierachical divisions within 
 the ASIC to improve connectivity\, a new fast analytical thermal simulator
  and also utilize simulated annealing with reinforcement learning (SARL) i
 n VLSI floorplanning for the first time. Our results are very successful d
 emonstrating an automated flow for generating thermal aware floorplans.\n\
 nMer information om händelsen: https://www.eit.lth.se/evenemang/exjobbspr
 esentation-thermal-aware-floorplan-techniques-asics
DTSTART;TZID=GMT:20260608T111500
DTEND;TZID=GMT:20260608T120000
LOCATION:E:2517
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