Exjobbspresentation: Multi-Phase Clock Generation for Programmable Broadband Delay Circuits

Exjobbet genomfördes vid Ericsson AB I Lund med handledare Fabien Mesquita (Ericsson), Pallavi Paliwal (Ericsson) och Baktash Behmanesh som akademisk handledare. Examinator: Pietro Andreani.

Many circuits in integrated-circuit design require a time-shifted or multi-phase clock. In time-interleaved ADCs, multiple phases enable a higher effective aggregate sampling rate without increasing the individual clock rate. In contrast, in SerDes links, bit throughput increases while keeping each lane at a lower base clock. In 5G and 6G wireless equipment, multiple phases can be used to drive a true time delay (TTD) block, enabling programmable broadband delays for applications ranging from beamforming to power-amplifier predistortion. This work targets the latter: a bank of phases at a fixed frequency clocks the sample-and-hold taps of a TTD network, where the selected phase sets the delay applied to the sampled signal. The achievable delay range and resolution are therefore set directly by the number of phases and their spacing, motivating a generator that produces many accurately spaced phases at RF. This thesis presents a duty-cycle-controlled multi-phase clock generator that achieves 90 fs cycle-to-cycle jitter at 5.64 mW of total system power.