Exjobbspresentation: Implementing In-Memory Digital Pre-Distortion Computation Architectures Using Ferroelectric Tunnel Junction Memristors

Today, digital pre-distortion (DPD) is the predominant technique for linearising the power amplifiers (PAs) used in telecommunication radio transmitters. However, conventional DPD implementations rely on power-hungry digital signal processing, making energy efficiency a critical concern. Compute-in-memory (CiM) architectures have demonstrated significant efficiency gains for simple computation data-intensive workloads such as neural network inference. Since DPD involves structurally similar computations, this thesis investigates whether CiM architectures can provide a more energy-efficient alternative for DPD implementation. Specifically, ferroelectric tunnel junction (FTJ) memristors are evaluated as the processing elements within the CiM array, owing to their nonlinear I-V characteristics, derived from its tunnelling nature.

Two simulation tools were employed. IBM's AIHWKit was used for accuracy simulations, and CiMLoop was used for power, performance, and area (PPA) analysis. Three DPD models of varying sizes were defined and evaluated across a range of hardware configurations, including different levels of programming noise, ADC resolution, and weight quantisation.

The accuracy simulations yielded promising results. Multiple hardware configurations achieved adjacent channel power ratio (ACPR) below -45 dB, a conservatively derived threshold based on 3GPP conformance specifications. The PPA results were less conclusive. Energy and area estimates could not be reliably compared to measured hardware due to the inherent limitations of simulation-based analysis. More critically, the per-sample inference latency was estimated at 1.42 µs, corresponding to a sampling frequency of 0.7 MHz. This falls far short of the GHz-range sampling rates required for real-time 5G DPD. This bottleneck was enforced by RC time constant estimation and noise analysis, which showed minimum FTJ read times in the range of hundreds of nanoseconds, fundamentally constraining throughput.

In summary, this thesis demonstrates that FTJ-based CiM architectures can achieve the accuracy required for DPD linearisation, but doesn't reach the throughput demands of real-time 5G operation.  Addressing this speed limitation remains the primary challenge for future development of this approach.

Exjobbet har genomförts på Ericsson i Lund. Handledare: Mattias Borg, Saeed Bastani och Ashkan Kalantari.