Exjobbspresentation: FPGA-Accelerated Constrained Control of a 6-DOF Robotic Manipulator

Real-time constrained control of robotic manipulators places strict computational demands on the underlying hardware. At typical industrial control rates, the controller must solve a constrained optimisation problem at every sampling instant without exception. General-purpose computing platforms running standard operating systems are poorly suited to this requirement, not because the underlying algorithm is slow, but because the operating system introduces scheduling delays that cannot be bounded or removed through software tuning alone. This problem grows more severe for multi-degree-of-freedom manipulators running constrained optimal control, where the optimisation problem scales quadratically with the number of joints and the prediction horizon. This thesis investigates Field-Programmable Gate Arrays (FPGAs) as an alternative execution platform for model predictive control (MPC) of a six degree-of-freedom robotic manipulator. The solver is moved into dedicated hardware logic, where timing is governed by the circuit itself rather than by an operating system scheduler. The algorithm implemented is an operator-splitting quadratic program (OSQP) solver based on the Alternating Direction Method of Multipliers (ADMM), realised using high-level synthesis with fixed-point arithmetic on a resource-constrained embedded Artix-7 FPGA, communicating with the host over a 100 Mbit/s Ethernet link. The work compares a CPU-based software solver against the FPGA implementation, evaluated through a hardware-in-the-loop framework using a simulated UR5 robot via ROS2 Humble and Gazebo 11. The CPU reference shows a mean solver latency of 5 404 μs and scheduler-induced timing spikes reaching 23 430 μs under load, failing the 1 ms real-time requirement on both counts. Every one of 1 000 consecutive calls exceeded the budget. The FPGA implementation addresses both problems at once. The solver core executes 25 ADMM iterations in 81 μs, a 66.7 times speedup over the CPU mean, and hardware execution removes OS non-determinism entirely, confirmed by a measured timing standard deviation of 0.00 μs across 100 consecutive calls. The complete round-trip over Ethernet, including communication, measures 1.7 to 1.8 ms, a substantial reduction from an initial UART-based implementation whose serial link alone consumed 19.6 ms per step. Hardware-in-the-loop validation over 60 test moves, including a 17-minute continuous endurance run, confirms joint tracking within one degree with zero communication failures.

Handledare: Victor Åberg

Examinator: Pietro Andreani