Exjobbspresentation: A Dynamic Priority DMA Scheduler with linear Ageing

Exjobbet genomförder på Ericsson med Alberth Arvidsson och Leo Bärring som handledare, Victor Åberg som akademisk handledare och Pietro Anderani som examinator.

This thesis deals with a Multi-Port DMA interfacing the system memory. The ports are bidirectional, capable of both reading and writing to the memory, but switching direction from e.g. write to read infers a overhead penalty. A scheduling algorithm which optimizes the schedule in terms of overhead, would increase the overall throughput. For that reason, a dynamic priority algorithm with linear ageing (DPLA) is introduced, and the performance and fairness characteristics are compared against a computationally simpler First Come First Served (FCFS) method. A synthesis of the designs is carried out and the cost of the designs are compared to see if the added complexity of a more sophisticated model can be justified in terms of throughput and fairness gains.

Over all test cases in different traffic patterns and load situations the DPLA method achieves a 0.51% throughput gain over the FCFS method as well as a 14.3% improvement in average latency per byte and a 21.0% improvement in worst case latency per byte, meaning that a scheduler with a higher throughput and more fair scheduling was achieved. On average the number of overhead cycles per completed jobs was reduced by 13.8%. The synthesis revealed that the implementation cost of the DPLA method was 25 times larger than for FCFS, indicating that the hardware implementation cost, outweighs the relatively small gains seen in throughput.