Exjobbspresentation: Address Generation Unit (AGU) for a Custom DSP Core

Exjobbet genomfördes vid Silicon Integrated Co., Ltd. Handledare på EIT var Baktash Behmanesh, examinator är Pietro Andreani. 

Highly efficient memory access is a critical bottleneck in modern Digital Signal Processors (DSPs). To eliminate the severe clock cycle penalties caused by software-based address manipulation, this thesis presents a custom Address Generation Unit (AGU) tailored for a proprietary DSP. By entirely offloading complex address calculations from the main data-path, the proposed AGU introduces advanced capabilities including post-modification, modulo, bit-reversal, and multi-dimensional addressing. Evaluated across typical DSP benchmarks (FFT, FIR, IIR, and Matrix Multiplication), the integrated AGU achieved at least a 50% reduction in execution clock cycles and substantial code size compression of up to 46.2%. Although pre-layout logic synthesis indicates a modest increase in physical area (10.3%) and peak power (16.0%), the drastic reduction in execution time yields a significant decrease in overall energy consumption per task, proving the design as a highly favorable and energy-efficient architectural enhancement.