Exjobbspresentation: A 10b 1GS/s Time-Interleaved SAR ADC With Digital Background Calibration

This thesis consists of two main parts: MATLAB-based theoretical analysis of a TI SAR ADC, and the design of a 10-bit 1 GS/s TI SAR ADC prototype with digital background calibration. For the TI ADC analysis, the effects of typical nonidealities, including offset, gain, and timing skew, are evaluated. In the circuit prototype, an 8-channel 125 MS/s SAR sub-ADC architecture is used. Each sub-ADC adopts a bootstrapped switch, 1-bit binary redundancy, and asynchronous timing logic to improve speed and linearity, together with foreground calibration based on parallel input transistors to reduce comparator mismatch. For the TI architecture, multiphase clock generation and VDLs are implemented. A digital background calibration scheme is then applied to correct channel mismatches. Offset and gain mismatches are corrected by an averaging method. Timing skew is addressed by a global autocorrelation method combined with an LMS algorithm, which iteratively adjusts the sampling phase through the VDLs. The design is implemented in STM 65 nm CMOS technology. In the typical process corner, at 27◦C with a 1.2 V supply, the circuit operates at an overall sampling rate of 1 GS/s and an input frequency of 497 MHz, with an SNDR of 58.8 dB and an SFDR of 67.9 dB before calibration. After background calibration, the performance reaches 58.8 dB SNDR and 67.9 dB SFDR. The total power consumption is 12.27 mW, and the corresponding FoM is 164.4 dB. The core area is 1400 um x 400 um.

Handledare: Baktash Behmanesh and Wenbo Li 

Examinator: Pietro Andreani