- Synopsys Design Compiler v2007.03 : Design
Synthesis
- Mentor Graphics ModelSim v6.3a
: VHDL and Verilog Simulation
- Cadence Encounter v7.1
: Floorplanning &
Place and Route.
The tools are briefly described below. For more
complete instructions, tutorials etc look
in the information for the course in which this process is used.
There are also more manuals
within the tools.
Setup
All the tools needed are initialized by one command which
should be run in an empty sub-
directory. A lot of setup and example files will be created
if they do not already exist. On
the department's computors the following command shall be used.
> source ~synopsys/v2007/u90_setup
The setup routine will create a file structure that looks
like this
StartDir
______________________|___________________
|
|
|
|
|
vhdl netlists
WORK
work soc
Use
StartDir as default location when running
Synopsys
or
ModelSim. Before using the
Encounter tool, descend into the library
soc. The
function of the other directories are
- vhdl
: folder for vhdl-files.
- netlists
: output files from synthesis
- work & WORK : storage libraries
for ModelSim and Synopsys.
Synthesis with Synopsys
The cell libraries available are
fsd0k_a_generic_core : 1.0V Standard Cells. LL, low-k,
RVT.
fsd0k_a_generic_core_1d0vtc.db : typical
case
fsd0k_a_generic_core_0d9vwc.db : worst case
fsd0k_a_generic_core_1d1vbc.db : best case
fod0k_b25_t25_generic_io : 2.5V IO-Pads. LL, low-k,
RVT.
fod0k_b25_t25_generic_io_tt1p2v25c.db
: typical
fod0k_b25_t25_generic_io_ff1p32vm40c.db : best
fod0k_b25_t25_generic_io_ss1p08v125c.db : worst
fsd0j_a_generic_core : 1.0V Standard Cell. LL, low-k,
HVT.
fsd0j_a_generic_core_tt1v25c.db
: typical case.
fsd0j_a_generic_core_ff1p1vm40c.db : best case.
fsd0j_a_generic_core_ss0p9v125c.db : worst case.
fsd0j_a_generic_core_1d2v : 1.2V Standard Cell. LL, low-k,
HVT.
fsd0j_a_generic_core_1d2v_tc.db : typical
fsd0j_a_generic_core_1d2v_bc.db : best
fsd0j_a_generic_core_1d2v_wc.db : worst
All the library files can be found at
$FAR90/<lib_name>. Quick
links to all the '.lib'- and
'.db' files required by synopsys exists in the directory
$FAR90/syn2007/libbar.
Make the
appropriate changes in the local
'.synopsys_dc.setup'.
Some more information regarding the libraries can be found at
$FAR90/doc/
.
The synthesis program is started by the command
design_vision
.
There is a small example that can be studied. Look in
the file
'vhdl/medianfilter_P.vhd' for
information on how to use the pads in the vhdl-file. Use
'source
comp.dv' to start the exe-
cution of the command file.
Simulation
Simulation is performed in the
ModelSim tool, which
can handle both vhdl and verilog
files. Simulation can be executed before or after synthesis.
The simulator tool
is started by the
command
'vsim'.
There is a small example command file that runs through an entire
simulation. This is executed
by typing
'vsim -do medfilt.cmd' at the shell prompt.
There is a lot of documentation available from the tool menues. Here
is a direct address to a
tutorial
$MODEL_SIM/docs/pdfdocs/modelsim_se_tut.pdf
Place'n'Route
The place-and-route of the construction
is performed by the Cadence tool Encounter.
It is started with the command 'encounter'.
Do not use an ampersand (&) here. The window
from which Encounter is started will serve as the
command input window.
The setup command will copy some setup- and
command files that executes an example design
in Encounter. The entire session is then launched
by the command 'source MedFilt.com' from
the command window. Naturally the commands are also available
from the tool menues.
As shown in the example pad placement file 'MedFilt.io'
the corner- and power pads can be in-
troduced in this file. There is no need to edit them into the
verilog file.
When the design is ready, it has to be saved
in a special format (stream) before it is sent for
fabrication. Invoke the command Design > Save
> GDS and fill in the names of the stream file
to be created and of the mapfile, far90_soc.map.