UMC 90nm Design Kit for Linux Platform


This is the new (vB15) design kit for the United Microelectronics 90nm CMOS process for use
on the Linux platform.

It has been installed and modified for 1.8V and Metal Option 13, Top Metal 32kA as
described in the design kit manual.

For information on how to use this process together with the digital tools look  here.


Initialization


The environment is initialized by the command

>  source /usr/local-eit/cad2/umc/umc90B15/setup

from the department's computors.

The Cadence tool can then be started with

> icfb &

The initialization command will copy some setup files  to the current catalog so a previously
empty directory should be used.

New (Cadence)libraries should be attached to the existing 'umc90nm' technology.


Documentation

In the library $UMC90 are some notes on the design kit.

G-9FD-LOGIC_MIXED_MODE90N-1P9M-LOW_K_UMK90FDKLMC-FDK-Ver.B15_PB.pdf
FDK_Application_Note_UMK90FDKLMC_B15_PB.pdf
FDK_User_Guide_V1_2.pdf
Release_Note_UMK90FDKLMC_B15_PB.pdf


More manuals describing the process in directory $UMC90/documents/<subdir>

TLR: Topological Layout Rules.
EDR: Electrical Design Rules.
Intercap: Interconnect Capacitance.
Masktool: Mask Tooling.


Design Checks

For design verification the Cadence Assura tool is used. If there is a menu-header labeled
Assura in the layout editor, the tool is avaiable. If not, help should be found.

The use of Assura to perform the checks is briefly described in the design kit manual.

Always finish with the Assura > Close Run command to shut down the verification tool in a
proper way.

Design Rule Check

Select Assura > Run DRC in the layout window. Then, in the form that pops up, at Technology
select umc90nm_DRC. Rule Set should be Option13_Top_Metal_3250. There is also a number
of runtime Switches for specific needs.

Select a Run Directory where the data- and log-files can be stored by the Run Name. Remember
that big designs implies big data sets.

When all is filled out, hit Apply !

The errors will then be presented in an easy-to-use browser.

Note that the manufacturing grid is 0.005 um. This means that no coordinate can have a higher resolution.
An ill effect  of this is that wires can not be angled diagonally without causing problems. The corners of
such a wire will be off grid and hence illegal. If slanted structures are needed, create them as polygons and
make sure that the angles are exactly 45 degrees. In order to have Assura check this kind of errors select
the avParameters 'flagNon45' and 'flagOffGrid'.


Quick LVS guide

Pins in the layout view has to be created as text labels ( Create > Label ) in the same layer as the  structure on
which it is put. Make sure it is completely enclosed by the wire or rectangle.

When LVS is started ( Assura > Run LVS ) a form will pop up. Make sure that the settings for the schematic
and layout source are correct. Select Technology umc90nm_LVS and Rule Set as above and click Apply.

Parasitic Extraction

The extraction of parasitic components on the layout is now operational. It can be executed after a LVS
by the command  Assura > Run RCX.
The result of the extraction should now be in the new view  av_extracted and can be used in a post-layout
simulation.



DRC  with Calibre 

It is also possible to run the design rule check with the Mentor Graphics tool Calibre.
Perform the following steps

Uncomment the line ';load(strcat(getShellEnvVar("MGC_HOME") "/lib/calibre.skl"))'
from the local '.cdsinit' file.

Use Calibre > Run DRC from the layout window. Fill in the DRC rules file
'$UMC90/RuleDecks/Calibre/DRC/G-DF-LOGIC_MIXED_MODE90N-1P9M2T1F-32.5KA-Calibre-drc-1.9-p2'
and a directory to store the files in.

Start the checking by clicking on Start DRC.

Some rules concerning the slot- and dummy blocking rules can be checked by the rules file
'G-DF-GENERATION90N-METAL-DUMMY_SLOT-1P9M2T1F-32.5KA-Calibre-drc-1.4-p1'
from the same directory.

Antenna Checks

For antenna checks use the file 'umc_ant_L90N_1P9M_calibre_V9' in Calibre. To fix use bridges in
higher metal or create a diode close to the gate to be protected. This can be accomplished by a contact
to n-diff (M1_NACTIVE) to the substrate outside n-well. The contact must be more than minimum
size.


Mixed-Mode Simulation

The standard cell libraries from Faraday are now available for design in the Cadence environment.
They show up in the Library Manager by these names

FOD0A_B25_T25_GENERIC_IO  : SP, lowK, RVt,  IO cells.
FSD0A_A_GENERIC_CORE        : SP, lowK, RVt, Standard Logic Cells


The libraries contain symbols and abstract layout that can be used in the schematic and layout editors.
Information regarding  the libraries can be found on the digital pages  for this process. Since there are
no schematic views with transistor symbols for the library cells they can not be simulated as usual by
the spectre simulator.

In order to simulate a design with the libraries, create a config view of the testbench and select the
spectreVerilog simulator among the templates. Then use this view to select how each cell is to be
simulated. The symbol view of the standard cell means that it will be simulated by the digital simulator.

Start the Analog Environment and set the simulator to spectreVerilog. Also check that the Options
File under 'Simulation > Options > Digital' is set to '/usr/local-eit/cad2/faraday/syn2009/verilog.opt'.

The default Interface Elements (umc90nm:MOS10_..) have been set for 1.0 V.