UMC 130nm Design Kit vA02


This is the latest design kit for the United Microelectronics 130nm process.

This page describes how to initialize the design environment and start the Cadence tool
for schematic and layout design.






Setup



From the department domain the environment is initialized by the command

> source /usr/local-eit/cad2/umc/u130a02/setup

And on the laboratory computers use

> inittde ana2019

When this is done the tool may then be started with the command

> virtuoso &


A number of files will be copied to the location from which Cadence is stared so
a previously empty directory should be used the ifrst time.



Documentation

In the library '$UMC130/docs/' there are some manuals about layout rules and
electrical parameters.

Information regarding the design kit can be found in $UMC130/doc
FDK_Application_Note_UM130FDKMFC0000OA_A02_PB.pdf
FDK_OA_User_Guide_V1_3.pdf
QA_Report_G-9FD-MIXED_MODE_RFCMOS13-1P8M-MMC_FSG_L130E-UM130FDKMFC0000OA-FDK-A02_PB.pdf
Release_Note_UM130FDKMFC0000OA_A02_PB.pdf


Cadence Documentation

The documentation viewer can be started directly from the tool or by one of the following commands

$CDSDIR/tools/bin/cdnshelp                # Cadence Main Tool
$MMSIM/tools/bin/cdnshelp                 # Analog Simulator



Pads

There is a small library with pads that have some esd protection. Just add the
following line to the local "cds.lib" file.

DEFINE Pads19 $UMC130/../Pads19


Design Checks

For design verification the tool Calibre from Mentor Graphics is used.

Design Rule Check

Select Calibre> Run DRC from the top menues in the layout window.

At Rules : DRC Rules File navigate to $UMC130/RuleDecks/Calibre/DRC and select
the file G-DF-GENERATION13-BEOL-1P8M2T-Calibre-drc-2.3-P5_20KA.

Also, select a Run Directory where the resulting files can be stored.

Click on the Run DRC button and await the result which is presented in a browser.

Repeat this procedure for the file G-DF-MIXEDMODE_RFCMOS13-1P8M2T-MMC-L130E_Calibre-drc-2.5-P1


Note that it is possible to store the settings in an runset file which makes it easier
the next time the program is started.

The final design should also pass a antenna rules check which is performed by the file
umc_ant_0.13um_1P8M2T-CALIBRE-DRC-P4.cal

Quick LVS guide

LVS is the process where the layout is compared with the schematic. This is achieved by
generating netlists from both sources which are then checked against each other.

For this to work the connection points in the layout has to be marked with the same names
as the pins in the schematic view.

Add these markers in the layer M1_CAD:TEXT to the layout view of the design by the help
of the commandCreate > Label

Start with Calibre > Run LVS and descend into $UMC130/RuleDecks/Calibre/LVS, then
select the file G-DF-MIXED_MODE_RFCMOS13-1P8M-MMC-FSG-L130E-CALIBRE-LVS-2.3-P10.txt.

Make sure that the box Export from schematic viewer at Inputs : Netlist is chosen.

Fill in the names of the power at LVS Options.

Parasitic Extraction

Only after a successful lvs run can the parasitc components be extracted from the layout.
Select Calibre > Run PEX to activate the program. Choose the file CalibrePEX from the
same place as before.

Fill in the power node names at PEX Options : LVS Options.

At Outputs Select the type of extraction that is to be run and make sure that Format: CALIBREVIEW
and Use Names From: SCHEMATIC is choosen.