Synplicity

Synplify Pro® is a logic synthesis tool for FPGAs (Field Programmable Gate Arrays) and
Complex PLDs (Programmable Logic Devices),  developed by Synplicity® of Sunnyvale,
California. For input,  the software uses high-level designs written in Verilog and VHDL
hardware description languages (HDLs). Using proprietary Behavior Extracting Synthesis
Technology® (B.E.S.T.)®,  the tool converts the HDL into small, high-performance, de-
sign netlists that are optimized for popular technology vendors.  Optionally, the software
can write post-synthesis  VHDL  and Verilog netlists that you can use to  verify functio-
nality through simulation.

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Synplify Premier v2010.03

This version has been installed and can be initialized by the command

tde> source /usr/local-eit/cad2/synopsys/sfpga2010/setup

The main tool is then launched by the command

> synplify_pro

Manuals can be found in the directory  $SYNOPSYS/doc .