----- Synopsys v2006.06 -----

The older version of this page can be found here.

Synthesis and Simulation

Synopsys is used to simulate and synthesize the design from a functional description in VHDL.
The design can then be placed and routed by Cadence Silicon Ensemble.

Before starting the synthesis tools, the technology has to be choosen. Different technologies do
not have the same size, speed, set of available gates, etc. The choise will be represented by va-
rious links, stored in set-up files, to cell-libraries that describe the selected technology. For the
moment these are available

    AMIS 0.35u    AMI Semiconductor v16.00

    AMS 0.35u    Austria Mikro Systeme v3.70

    UMC 0.13u    United Microelectronics Company. Faraday Libraries. NOT READY YET !

PrimeTime A timing and power analyzer setup to work with UMC 130nm.

There is an exstensive set of manuals to be studied for a deeper understanding of the tools. The
predefined commands sold ( and simsold for the simulator ) from the window in which the tools
were initialized, will launch the reader.

There are som major changes in this version. The tools/commands vhdlan and design_analyzer
works as before but vhdldbx does not exist any more.

Use the scs command to generate an simulation executable which can then be interactively simu-
lated in the VirSim tool.

> scs -exec /tmp/agurk work.cfg_syn_medianfilter_tb

This command creates the executable 'agurk' in the temporary area (default name is ./scsim) from
the configuration in the library 'WORK'. The created file can also be executed and simulation
commands fed in on a command line while the results are stored in a database for later viewing.

The command scirocco starts the simulator GUI in which the created executable can be read in
and the design simulated or stored results from earlier sessions can be studied. On the efd-machines
it might help to use scirocco +sim+./scsim so that the executable can be found.