ST Microelectronics 65nm CMOS v5.4

This page describes how to use the new design kit for analog design.

This design kit must be used for all fabrications in the future. The older one is now obsolete.

As usual the access to this PDK is restricted to the special group of Linux
computers  'marconi', 'motala', and 'popov'.  Those without a local account on these machines are
not able to use this design kit.

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Setup procedure

The environment is defined by a setup script which is called by the command

> source /usr/hidden/cmp/c65v54/setup


The first time this is run, the script will also copy some files that are necessary for proper
function of the design kit. Afterwards the Cadence design tool can be started by

> virtuoso &


Connect new libraries to technology cmos065 .

Simulation is a little more complicated than usual. Start the procedure by the command
ArtistKit > Setup Corners from the Analog Environment window. Here, the wanted model
files can be selected. After the selection has been confirmed by Save Model File the si-
mulation can be performed normally. See more in the documentation!

Documentation

There is also an extensive set of maunuals which can be read by a browser which
is started by the command

> unidoc &

Extra Pads

There is a set of small rf-pads created by Carl. They can be accessed after including the
following line in the 'cds.lib' file.

'DEFINE CBlib065oa /usr/local-eit/cad2/cadence/CBlib065oa'

Design Rule Check

It is possible to verify that the layout rules are fulfilled in the design are fulfilled. This is
done by the tool Calibrefrom Mentor Graphics. It is started from the Calibre
menu in the layout window.

After selecting Run nmDRC in the Calibre menu two new windows are created. In the one
labeled Customer Settings some switches that affect the checking can be modified. From
the other, Calibre Interactive, the drc run can be started with the button Run DRC. The
errors are then presented in an easy to use viewer.

Calibre LVS

Calibre > Run nmLVS will start Calibre for a Layout versus Schematic check.  Here a
netlist created from the schematic view will be compared to an extracted netlist from the
layout. All component sizes and connections will be compared and discrepancies reported.

Under Rules check that $U2DK_CALIBRE_LVS_DECK is filled in. At Inputs infor-
mation of the cell to be tested can be found.

Run LVS will start the check.

Global power nets, like vdd!, will confuse Calibre and will be reported as wrong.

Select the button Ingore layout and source pins ... at LVS Options : Supply to avoid
the problem with the global supply nets.

Calibre PEX

The Parasitic EXtraction will calculate the parasitic components in the layout and
create a 'calibre' view that can be simulated in order to gauge their impact on the design.

Select CALIBREVIEW and Names From LAYOUT at Outputs. The type of extraction
(R, L, C) can also be chosen here.

At the end, when the Calibre View Setupwindow pops up, it is important to select Schematic
as Calibre View Type.

The resulting view (calibre) can then be used by a config test bench as usual.

Extra Options Check

To check that no illegal options are used in the layout there is an extra check procedure for
which the ancient Diva rule checker is used.

Start by copying the file $STM065RF/CMOS065_options.diva to the current directory.

Choose Verify > DRC... from the layout window and fill in the name of the file at Rules File.

The selected options are now listed as errors in the main window. Compare these with the chosen options and make sure they match.

Tiling

The process of Tiling will make sure that the design will satisfy the density rules by adding
small structures of the layers that are not frequent enough.

The process starts by typing the command 'calibrerun -smart_tiling' and a Calibre> window
will appear. Click OK in the Customization Settings window.

At Inputs in the remaining window setRun : DRC(Hierarchical), pick the layout filei from
the previous DRC run or generate it anew. Also fill in the name of the Top Cell and hit Run DRC.

This will create two stream files, tiles_BE.gds and tiles_FE.gds which can be imported
(CIW: File > Import > Stream) to a library.

The resulting cells (<Top Cell>_TILES.BE and ...FE can now be instantiated in
the design for a new run of DRC.