STMicroelectronics 65nm CMOS v5.3.6

[Nov 2012]

This is the newest design kit for the STM 65nm standard cmos process. The older version
should not be used anymore.

There is also a special RF design kit  elsewhere.

This page contains instructions on how to use the kit together with the analog
design tools on the Linux platform only. For use with the synthesis tools, have
a look here for a short description.


Notes

Old desins that are to be reused must be converted to the new database format. For information
about how to do this; type the command "cdb2oa -help", after initialization.



Setup procedure

The environment is defined by a setup script which is called by the command

> source /usr/local-eit/cad2/cmpstm/stm065v536/setup


The first time this is run, the script will also copy some files that are necessary for proper
function of the design kit. Afterwards the Cadence design tool can be started by

> virtuoso &


Connect new libraries to technology cmos065 .

Simulation is a little more complicated than usual. Start the procedure
by the command Tools > Setup Corners from the Analog Environment
window. Here, the wanted model files can be selected. After the selection
has been confirmed by Save Model File the simulation can be run
normally. See more in the documentation!


Documentation

There is also an extensive set of maunuals which can be read by a browser which
is started by the command

> unidoc &

Cadence Documentation

The documentation viewer can be started directly from the tool or by one of the following commands

$CDS_INST_DIR/lnx/tools/bin/cdnshelp # Cadence Main Tool
$CDS_MMSIM_DIR/tools/bin/cdnshelp                  # Analog Simulator

Extra Pads

There is a set of smaller rf-pads built by Carl. They can be accessed after including the
following line in the './cds.lib' file.

'DEFINE CBlib065oa /usr/local-eit/cad2/cadence/CBlib065oa'


Chip Assembly Router

The Autorouter is now available from the Layout XL tool (Routing > Autorouting).

The mauals for this can be read by $ICC/share/bin/cdsdoc .

Design Rule Check

It is now possible to verify that the layout rules for the design are fulfilled. This is done
by the tool Calibre from Mentor Graphics. It is started from the Calibre menu  header
in the layout window. If this does not exist, try removing the local .cdsinit file and redo
the initialization procedure where an new file wiil be created.

After selecting Run DRC in the Calibre menu two new windows are created. In the one
labeled Customer Settings some switches that affect the checking can be modified. From
the other, Calibre Interactive, the drc run can be started with the button Run DRC. The
errors are then presented in an easy to use viewer.


Calibre LVS

Calibre > Run LVS will start Calibre for a Layout versus Schematic check.  Here a
netlist created from the schematic view will be compared to an extracted netlist from the
layout. All component sizes and connections will be compared and discrepancies reported.

Under Rules check that $U2DK_CALIBRE_LVS_DECK is filled in. At Inputs infor-
mation of the cell to be tested can be found.

Run LVS will start the check.

Global power nets, like vdd!, will confuse Calibre and will be reported as wrong.

Select the button Ingore layout and source pins ... at LVS Options : Supply to avoid
the problem with the global supply nets.

Calibre PEX

The Parasitic EXtraction will calculate the parasitic components on the layout and
create a 'calibre' view that can be simulated in order to gauge their impact on the design.

Select CALIBREVIEW and Names From LAYOUT at Outputs. The type of extraction
(R, L, C) can also be chosen here.

At the end, when the Calibre View Setup window pops up, it is important to select Schematic
as Calibre View Type.

The resulting view (calibre) can then be used by a config test bench as usual.


Extra Options Check

To check that no illegal options are used in the layout there is an extra check procedure for
which the ancient Diva is used.

Start by copying the file $STM065_DIR/CMOS065_options.diva

Choose Verify > DRC... from the layout window and fill in the name of the file at Rules File.

The selected options are now listed as errors in the main window. Compare these with the intended
ones and make sure they match.



Importing a stream file

Follow this procedure to import the design, as a stream-file, from Encounter.

  * Create a Cadence library, to hold the design, and attach it to the 'cmos065' technology.
  * Execute the command 'File > Import > Stream'. Fill in Input File and the name of the newly
     created library.
  * Then click on Show Options and select Libraries. Select and move the libraries used to the
     right window, labeled Reference Libraries. Do not forget the libraries added by Encounter.
     For the example design these libraries are used CORE65LPHVT,  IO65LPHVT_SF_1V8_50A_7M4X0Y2Z,
     IO65LP_SF_BASIC_50A_ST_7M4X0Y2Z, and PRHS65.
   * Click on Apply and select a file name, in which  to store the library information, in the window that opens.