ST Microelectronics 65nm RF CMOS v5.3.6
[Nov 2012]
This page describes how to use the new RF design kit for
analog design.
This design kit must be used for all fabrications in the future.
The
older one is now obsolete.
The access to this PDK is very restricted so it is only available
from the Linux computer
named 'marconi' in the secret cluster. It will probably not work
on 'radiocad'. People without
a local account on these machines can not use this design kit.
Also
Cadence 6.1.5 is used. This means that
old designs that are to be reused have to be
coverted to the new database format. Type "cdb2oa -help" to find out how.
Setup procedure
The environment is defined by a setup script
which is called by the command
>
source /home/marconi/cmp/c65rf536/setup
The first time this is run, the script will also
copy some files that are necessary for proper
function of the design kit. Afterwards the
Cadence design tool can be started by
> virtuoso &
Connect new libraries to technology
cmos065 .
Simulation is a little more complicated than usual.
Start the procedure by the command
ArtistKit > Setup Corners from the
Analog Environment
window. Here, the wanted model
files can be selected. After the selection has been confirmed
by
Save Model File the si-
mulation can be performed normally. See more in the documentation
!
Documentation
There is also an extensive set of maunuals which can be
read by a browser which
is started by the command
>
unidoc &
Extra Pads
There is a set of small rf-pads created by Carl. They can be accessed
after including the
following line in the
'cds.lib' file.
'DEFINE CBlib065oa /usr/local-eit/cad2/cadence/CBlib065oa' (
local-tde
on radiocad)
Extra Options Check
To check that no illegal options are used in the layout there is an extra
check procedure for
which the ancient
Diva is used.
Start by copying the file
$STM065RF/CMOS065_options.diva
Choose
Verify > DRC... from the layout window and fill in the
name of the file at
Rules File.
The selected options are now listed as errors in the main window. Compare
these with the intended
ones and make sure they match.
Only basic schematic design and simulation have been tested yet.