STMicroelectronics 65nm CMOS v5.3.6

[Jan 2013]
For this 65nm CMOS process there is a set of libraries containing standard cells and
input/output pads. These can be used for design synthesis, functional verification, and
final floorplanning with a set of tools that is available.

Synopsys Design Compiler v2011.09 : Design Synthesis
Synopsys PrimeTime v2011.12 : Power and Timing Analyzer
Mentor Graphics ModelSim v6.6 : VHDL and Verilog Simulation
Cadence Encounter v8.1 : Floorplanning & Place and Route.

The tools are briefly described below. For more complete instructions, tutorials etc look
in the information for the course in which this process is used. There are also more manuals
within the tools. How to start the manual reader is described along with the instructions
for analog design.

Setup

All the tools needed are initialized by one command which should be run in an empty sub-
directory. A lot of setup and example files will be created if they do not already exist. On
the department's computors the following command shall be used.

> source /usr/local-eit/cad2/cmpstm/stm065v536/digsetup

An even newer setup script 'newdig' in the same location will initialize more modern versions
of the tools mentioned above. ModelSim has been replaced by Questa. Also the tools Encounter
Library Characterizer and Encounter RTL Compiler have been included. For more information
about these utilize the documentation readers

'$ETSDIR/tools/bin/cdnshelp'

'$RTLDIR/tools/bin/cdnshelp'

The new script 'digsetup15' will provide Encounter v13, Synopsys v2013, and QuestaSim v10.

Now, the Synopsys tetraMax is also included. It is started by the command 'tmax'.

The setup routine will create a file structure that looks like this

Use StartDir as default location when running Synopsys or ModelSim. Before using the
Encounter tool, descend into the library soc. The function of the other directories are

vhdl : folder for vhdl-files.
netlists : output files from synthesis
work & WORK : storage libraries for ModelSim and Synopsys.

Synthesis with Synopsys

There are several cell libraries available. The ones used in the small example are

CORE65LPHVT : Standard Cells.
IO65LPHVT_SF_1V8_50A_7M4X0Y2Z : Input output cells.

If others are to be used changes have to be performed in the setup file
.synopsys_dc.setup as usual. There are an extensive set of different lib files for various
conditions to choose among. Check the manuals carefully.

The synthesis program is started by the command design_vision .

The small example is started by the command 'source comp.dv' .

Simulation

Simulation is performed in the ModelSim tool, which can handle both vhdl and verilog
files. Simulation can be executed before or after synthesis. The simulator tool is started by the
command 'vsim'.

There is a small example command file that runs through an entire simulation. This is executed
by typing 'vsim -do medfilt.cmd' at the shell prompt.

There is a lot of documentation available from the tool menues. Here is a direct address to a
tutorial $MODEL_SIM/docs/pdfdocs/modelsim_se_tut.pdf

PrimeTime

The creator of these pages knows nothing of PrimeTime. A small setup file is created during startup.

Place'n'Route

The place-and-route of the construction is performed by the Cadence tool Encounter.

It is started with the command 'velocity'. Do not use an ampersand (&) here. The window
from which Encounter is started will serve as the command input window.

The setup command will copy some setup- and command files that executes an example design
in Encounter. The entire session is then launched by the command 'source MedFilt.com' from
the command window. Naturally the commands are also available from the tool menues.

In the file 'MedFilt.config' the library (*.lef) files are read into the encounter tool. These have
to match the ones used in the synthesis of the design. For the lef-files in the example there are quick
links to them. For other libraries look for the file in '<library>/CADENCE/LEF/'.

Some extra libraries are introduced at this stage. They hold cells that are required by
the tool to finish the design.

PRHS65 : Core filler cells. Decoupling cells. Substrate strap cells.
IO65LP_SF_BASIC_50A_ST_7M4X0Y2Z : Corner pads, power pads, filler pads.

As shown in the example pad placement file 'MedFilt.io' the corner- and power pads can be in-
troduced in this file. There is no need to edit them into the verilog file.

When the design is ready, it has to be saved in a special format (stream) before it is sent for
fabrication. Invoke the command Design > Save > GDS and fill in the names of the stream file
to be created and of the mapfile, st65_soc.map.