Investigation of Formal Verification Method for Clock and Reset Generation

Bin Wang () och Zhenzhong Xi ()

Sammanfattning

Designing and verifying Finite State Machines (FSMs) is crucial in the development of digital integrated circuits. The challenges faced by traditional methods– RTL (Register Transfer Level) and UVM (Universal Verification Methodology) are becoming increasingly severe in more complex designs. HLS (High-Level Synthesis) and FV (Formal Verification) provide us with a new approach to reduce development time and enhance robust performance. This research will conduct qualitative and quantitative analyses of the characteristics, advantages and disadvantages of the new and old methods from proposing the design to the final verification.

Handledare: Liang Liu (EIT)
Examinator: Erik Larsson (EIT)