My current research project is a post-doctoral project titled "Wireless communication transmitter architectures with high efficiency and linearity".
The main goal of this project is to investigate and design suitable architectures for largely digital transmitters at radio frequencies, suitable for wireless communication systems, with the aim of high efficiency and high linearity. In order to achieve this, architectures using switching power amplifiers are investigated. These power amplifiers need to be driven by a suitable building block that easily transforms the digital baseband signal to a control signal. Building blocks to be investigated are pulse-width modulators and sigma-delta modulators.
One of the main problems of today’s mobile communication systems is the power consumption in the power amplifier (PA) at radio frequencies (RF). This component determines much of the talking time of handsets, and has a large impact on the power consumption in base stations. Moreover, mobile communication standards are evolving towards increased demands on the linearity of the transmitter, which to a large extent also is determined by the power amplifier.
Power amplifier configurations offering both a high power consumption efficiency and a high linearity are so-called switching PAs, commonly used in audio amplifiers (low frequencies) but rather uncommon at RF. This is due to several reasons. Firstly, the modulator controlling the switching PA must switch at high frequencies, typically at least 4 x RF. This increases the power consumption in the modulator. Secondly, the output power of the PA may be partly reflected back into the power amplifier, depending on the filter used after the PA. This creates disturbance of the signal. Thirdly, mobile communication signals within a specific standard (such as 3G) typically range over several tens to several hundreds of MHz. Filter limitations are such that an output filter must cover the full band, and that possible noise and distortion cannot be filtered out without additional filters. This is undesirable since additional filters add to the
complication of the transmitter and may increase assembly costs.
One option to avoid high modulator frequencies is to split the RF signal into an envelope (low frequency) and a phase (high frequency) part, and use the modulator on the low-frequency part of the signal. This is similar to the classical Envelope Elimination and Restoration (EER) technique, and is being investigated in research applications
in this field.
A power amplifier has been implemented using a discrete GaN HEMT power device and passive input and output networks. This amplifier has been used for Pulse Width Modulation by Variable Gate Bias. This architecture avoids modulation of the power supply, and thus a DC-DC converter; The envelope signal is used to change the gate bias level, while the phase signal is applied to the gate. Measurements show that the maximum drain efficiency of this architecture is 86%, for an output power of 36dBm (VDD = 18V, finRF = 400MHz; see figure 1). The efficiency drops for reduced output power.
Fig. 1. A GaN HEMT power amplifier, and measured output power and drain efficiency for the PWMVGB architecture.
Class-D CMOS power amplifiers have been measured as well, based on a similar architecture; the gate bias level of the inverters are changed with the envelope signal (finRF = 1.5GHz). This architecture has been compared to an EER-like architecture, where VDD is varied instead (see figure 2).
Fig. 2. Chip micrographs of the CMOS class-D power amplifiers, and measured output power and drain efficiency for the PWMVGB and EER architectures for the 6dBm PA. In the last plot, the efficiency is plotted vs. the output power for both architectures.
For this PA the maximum drain efficiency is 39%, for an output power of 5.7dBm. Losses in these amplifiers include switching (dynamic) losses, static losses, direct-path losses, harmonic losses and losses in the output matching network. Due to the high switching frequency, dynamic losses are likely to dominate, especially for reduced VDD.
4. Next steps
The next steps in this project are to investigate different PA architectures as well as other transmitter architectures suitable for polar transmitters.