Publikationer

• Journal Articles (4)
• Conference Papers (Peer reviewed) (8)
• Conference Papers (5)

1. H. Sjöland, J. B. Anderson, C. Bryant, R. Chandra, O. Edfors, A. Johansson, N. Seyed Mazloum, R. Meraji, P. Nilsson, D. Radjen, J. Rodrigues, Y. Sherazi, V. Öwall:
   A receiver architecture for devices in wireless body area networks
   Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2012. (BibTeX) (More info)
2. Y. Sherazi, J. Rodrigues, O. Akgun, H. Sjöland, P. Nilsson:
   Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
   Microprocessors and Microsystems, 2012. (BibTeX) (More info)
3. P. Meinerzhagen, Y. Sherazi, A. Burg, J. Rodrigues:
   Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
   Journal of Emerging and Selected Topicss in Circuits and Systems, Vol. 1, No. 2, pp. 173-182, 2011. (BibTeX) (More info)
4. Y. Sherazi, S. Asif, E. Backenius, M. Vesterbacka:
   Reduction of substrate noise in sub clock frequency range
   IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, No. 6, pp. 1287-1297, 2010. (BibTeX) (More info)

1. R. Meraji, Y. Sherazi, J. B. Anderson, H. Sjöland, V. Öwall:
   Analog and Digital Approaches for an Energy Efficient Low Complexity Channel Decoder
   ISCAS 2013, Beijing, China, 2013-05-19. (In press) (BibTeX) (More info)
2. P. Meinerzhagen, O. Andersson, B. Mohammadi, Y. Sherazi, A. Burg, J. Rodrigues:
   A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
   IEEE, ESSIRC 2012, Bordeaux, France, 2012-09-17/2012-09-21. (BibTeX) (More info)
3. B. Mohammadi, Y. Sherazi, J. Rodrigues:
   Sizing of Dual-VT Gates for Sub-VT circuits
   IEEE Subthreshold Microelectronics, Waltham, Massachusetts, USA., 2012-10-09/2012-10-10. (In press) (BibTeX) (More info)
4. Y. Sherazi, P. Nilsson, H. Sjöland, J. Rodrigues:
   A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
   IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Seville, Spain, 2012-12-09/2012-12-12. (In press) (BibTeX) (More info)
5. O. Andersson, Y. Sherazi, J. Rodrigues:
   Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
   IEEE, NORCHIP, Lund, Sweden, 2011-11-14/2011-11-15. (BibTeX) (More info)
6. Y. Sherazi, P. Nilsson, O. Akgun, H. Sjöland, J. Rodrigues:
   Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
   2011 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE International Symposium on Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil, pp. 837-840, 2011-05-16/2011-05-19. (BibTeX) (More info)
7. P. Meinerzhagen, O. Andersson, Y. Sherazi, A. Burg, J. Rodrigues:
   Synthesis Strategies for Sub-VT Systems
   IEEE, 20th European Conference on Circuit Theory and Design. ECCTD 2011, Linköping, Sweden, 2011-08-29/2011-08-31. (BibTeX) (More info)
8. Y. Sherazi, J. Rodrigues, O. Akgun, H. Sjöland, P. Nilsson:
   Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
   NORCHIP, Tampere, Finland, 2010-11-15/2010-11-16. (In press) (BibTeX) (More info)

1. O. Andersson, Y. Sherazi, B. Mohammadi, P. Meinerzhagen, A. Burg, J. Rodrigues:
   Integration of Full-Custom Cells in a Standard-Cell Based Flow
   CDNLive! EMEA, Munich, 2012-05-14/2012-05-16. (BibTeX) (More info)
2. R. Meraji, Y. Sherazi, J. Rodrigues:
   Physical implementation of analog circuits assisted by conventional digital place and route methods
   CDNLive! EMEA, Munich, Germany, 2011-05-03. (In press) (BibTeX) (More info)
3. Y. Sherazi, J. Rodrigues, P. Nilsson:
   Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS
   Swedish System On Chip (SSoCC'10), Vildmarkshotellet, Kolmården, Sweden, 2010-05-03/2010-05-04. (BibTeX) (More info)
4. Y. Sherazi, J. Rodrigues, P. Nilsson:
   Power consumption in digital filter architectures in 65 nm CMOS technology
   2010 GigaHertz Symposium, Lund, 2010-03-09. (BibTeX) (More info)
5. Y. Sherazi, A. Fahsold, J. Rodrigues, P. Nilsson:
   A study on leakage minimization by RBB in 65 nm CMOS
   Swedish System-on-Chip Conference 2009 (SSoCC'09), Arild, Sweden, 2009-05-04/2009-05-05. (BibTeX) (More info)