Publikationer

• Journal Articles (8)
• Conference Papers (Peer reviewed) (18)
• Conference Abstracts (1)

1. P. Lu, A. Liscidini, P. Andreani:
   A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
   IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, No. 7, pp. 1626-1635, 2012. (BibTeX) (More info)
2. P. Lu, H. Sjöland:
   A 5GHz 90-nm CMOS all digital phase-locked loop
   Analog integrated circuits and signal Processing, Vol. 66, No. 1, pp. 49-59, 2011. (BibTeX) (More info)
3. C. Huang, P. Lu, N. Li, F. Ye:
   A 4 GHz ring oscillator based on dual-feedback loops with PVT deviation adaption
   Journal of Fudan University, Vol. 46, No. 1, pp. 70-76, 2007. (BibTeX) (More info)
4. D. Chen, P. Lu, L. Li, J. Ren:
   A low-jitter clock generator for HDTV
   Microelectronics, Vol. 37, No. 1, pp. 147-150, 2007. (BibTeX) (More info)
5. P. Lu, Y. Wang, L. Li, J. Ren:
   A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet
   Journal of semiconductors, Vol. 27, No. 1, pp. 137-142, 2006. (BibTeX) (More info)
6. P. Lu, Y. Wang, L. Li, Z. Zheng:
   A 1.8v low-jitter clock generator for 1000 Base-T Ethernet Transceiver
   Journal of Fudan University, Vol. 44, No. 1, pp. 155-161, 2005. (BibTeX) (More info)
7. P. Lu, Y. Wang, L. Li, J. Ren:
   A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver
   Journal of Semiconductors, Vol. 26, No. 8, pp. 1641-1645, 2005. (BibTeX) (More info)
8. P. Lu, Z. Zheng:
   Delay-locked loop and its applications
   Research & progress of solid state electronics, Vol. 25, No. 1, pp. 81-88, 2005. (BibTeX) (More info)

1. D. Ye, P. Lu, P. Andreani, R. v. d. Zee:
   A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
   ISCAS, Beijing, China, 2013-05-19. (In press) (BibTeX) (More info)
2. P. Lu, P. Andreani, A. Liscidini:
   A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
   IEEE RFIC, Seattle, Washington, USA, 2013-06-02. (In press) (BibTeX) (More info)
3. P. Lu, Y. Wu, P. Andreani:
   A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
   ISCAS, Seoul, Korea, pp. 2593-2596, 2012-05-20. (BibTeX) (More info)
4. P. Lu, A. Liscidini, P. Andreani:
   A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
   NORCHIP, Danmark, 2012-11-12. (In press) (BibTeX) (More info)
5. M. Abdulaziz, M. Shakir, P. Lu, P. Andreani:
   A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
   NORCHIP, Lund, Sweden, 14-15 Nov. 2011. (BibTeX) (More info)
6. P. Lu, P. Andreani, A. Liscidini:
   A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
   ESSCIRC, Helsinki, Finland, pp. 459-462, 2011-09-16. (BibTeX) (More info)
7. Y. Wu, X. Liu, D. Ye, V. Viswam, L. Zhu, P. Lu, D. Radjen, H. Sjöland:
   A 0.13µm CMOS ?? PLL FM Transmitter
   Norchip, Lund, Sweden, 2011-11-14/2011-11-15. (BibTeX) (More info)
8. M. Shakir, M. Abdulaziz, P. Lu, P. Andreani:
   A mixed mode design flow for multi GHz ADPLLs
   NORCHIP, LUND, Sweden, 14-15 Nov. 2011. (BibTeX) (More info)
9. Y. Wu, P. Lu, P. Andreani:
   A Digital PLL with a Multi-Delay Coarse-Fine TDC
   Norchip, Lund, Sweden, 2011-11-16. (BibTeX) (More info)
10. P. Lu, P. Andreani:
    A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS
    Norchip, Tempere, Finland, 2010-11-16. (BibTeX) (More info)
11. P. Lu, H. Sjöland:
    A 5GHz 90-nm CMOS all digital phase-locked loop
    ASSCC, Taiwan, pp. 65-68, 2009-11-18. (BibTeX) (More info)
12. P. Lu, D. Chen, J. Ren:
    A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator
    IEEE international SOC conference, SOCC 2009, Belfast, Northern Ireland, pp. 39-42, 209-09-09/2009-09-11. (BibTeX) (More info)
13. P. Lu, H. Sjöland:
    A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM
    Norchip 2008, Tallinnn, 2008-11-17. (BibTeX) (More info)
14. P. Lu, F. Ye, J. Ren:
    A 4.6GHz PLL with automatic frequency calibration based on multiple-pass ring oscillator
    The IET International Conference on Wireless, Mobile and Multimedia Networks, 2006-11-06/2006-11-09. (BibTeX) (More info)
15. C. Tao, P. Lu, N. Li:
    A 12-bit 125-MHz segmented current-steering DAC for communication application
    The IET International Conference on Wireless, Mobile and Multimedia Networks, 2006-11-06/2006-11-09. (BibTeX) (More info)
16. P. Lu, F. Ye, J. Ren:
    A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet
    IEEE International Symposium on Circuits and Systems, ISCAS 2006, Island of Kos, Greece, pp. 2481-2484, 2006-05-21/2006-05-24. (BibTeX) (More info)
17. C. Tao, L. Yang, N. Li, P. Lu:
    A 1.8V transmitter for 10/100 Mbps Ethernet physical layer
    The 6th International Conference on ASIC, ASICON 2005, Shanghai , China, pp. 415-418, 2005-10-24/2005-10-27. (BibTeX) (More info)
18. P. Lu, Y. Wang, L. Li, J. Ren:
    A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver
    The 6th International Conference on ASIC, ASICON 2005, Shanghai, China, pp. 431-434, 2005-10-24/2005-10-27. (BibTeX) (More info)

1. M. Abdulaziz, M. Shakir, P. Lu, P. Andreani:
   A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
   GigaHertz Symposium 2012, Frösundavik, Stockholm, Sweden, 2012-03-06/2012-03-07. (BibTeX) (More info)