All-digital Phase-Locked Loop design
Low phase noise local oscillator signals are needed in cellular communication systems. In today’s cellular phones those signals are typically generated by an analog phase-locked loop (PLL) based frequency synthesizer, which is integrated on the same chip as the radio transceiver. To achieve low enough phase noise, however, the analog PLL typically uses off-chip loop filter components.
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process, as shown in Fig.1. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. The core area is 0.33mm2 and the current consumption is 30mA from a 1.2V supply.
Fig.1 Block diagram of ADPLL
In traditional TDCs, all the delay cells are matched to be as equal as possible. Although the phase error pulse width may span a full reference period during the acquisition process, the pulses are very short when the PLL is in the locked state. This means that only a small part of the inverters in the TDC are active in maintaining the feedback. In terms of quantization noise, the smallest inverter delay is preferred for these inverters, located at the beginning of the delay line. The TDC noise contribution, within the loop bandwidth, at the ADPLL RF output is
Since most of the TDC inverters are far away from the head and thus not important for noise performance, their delay time shouldn’t be restricted by the requirements of equation (1). A new TDC with different delay-time cells is therefore used. As illustrated in Fig.2, the complete delay chain has been divided into three segments. The fist segment has the shortest delay-time cells, which determines the TDC quantization noise in the locked state. The other two segments use longer delay-time cells by adding load MOS capacitors to the inverter output nodes. An alternative for reduced power consumption would be to instead use current-starved inverters to increase the delay time.
Fig.2 TDC with uneven delay cells
The ADPLL is implemented in a 90-nm CMOS process, and the chip microphotograph is shown in Fig. 3. The total active area is 0.33mm2 (excluding pads), of which the LC-tank based oscillator occupies about 0.2mm2.
Fig.3 Die photo of ADPLL
A separate PFD with two TDCs was also fabricated to test the characteristics of the digital phase detection using uneven delay lines. The circuit was measured using two Rohde&Schwarz SMIQ signal generators producing two 300MHz tones, with one tone fed to each of the phase detector inputs. The generators used the same time reference, and the phase offset was then changed on one of the generators. Fig.4 shows the measured digitized output v.s. input phase error (time interval). There are obviously three different slopes on the curve. When the phase error is small, the average delay time is 13.6ps. In the next two banks, the delay time is 18.3ps and 43.3ps, respectively.
Fig.4 Measured TDC characteristic
The complete ADPLL was tested with a reference input clock signal of 322.5MHz from an HP 8642B signal generator. The measured output is a divided-by-2 clock from the DCO output. The closed-loop phase noise with/without ΔΣ fractional control was measured by a Europtest PN9000 phase noise test system, see Fig.5. The phase noise is -102dBc/Hz@100kHz and -125dBc/Hz@1MHz when the measured divided-by-2 carrier is 2.58GHz.
Fig.5 Measured closed-loop phase noise of 2.58GHz