Publications

• Books (1)
• Book Chapters (6)
• Journal Articles (15)
• Conference Papers (Peer reviewed) (72)
• Conference Papers (14)
• Dissertations (1)
• Miscellaneous (3)
• Popular Science Papers (5)

1. E. Larsson:
   Introduction to Advanced System-on-Chip Test Design and Optimization
   Frontiers in Electronic Testing, ISBN 1-4020-3207-2, Springer, 2005. (BibTeX) (More info)

1. D. Nikolov, M. Väyrynen, U. Ingelsson, E. Larsson, V. Singh:
   Optimizing Fault Tolerance for Multi-Processor System-on-Chip
   ISBN 1609602129, Information Science Publishing, 2010. (BibTeX) (More info)
2. A. Larsson, U. Ingelsson, E. Larsson, K. Chakrabarty:
   Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
   ISBN 1609602129, Information Science Publishing, 2010. (BibTeX) (More info)
3. E. Larsson, C. P. Ravikumar:
   Power-Aware System-Level DfT and Test Planning
   ISBN 978-1-4419-0927-5, Springer, 2009. (BibTeX) (More info)
4. E. Larsson, Z. Peng:
   An Integrated System-on-Chip Test Framework
   pp. 439-454, ISBN 978-1-4020-6487-6, Springer, 2008. (BibTeX) (More info)
5. E. Larsson, S. Edbom:
   Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
   IFIP International Federation for Information Processing, pp. 221-244, ISBN 978-0-387-73660-0, Springer, 2007. (BibTeX) (More info)
6. E. Larsson, Z. Peng:
   An Integrated Framework for the Design and Optimization of SOC Test Solutions
   Frontiers in Electronic Testing, pp. 21-36, ISBN 1-4020-7205-8, Kluwer Academic Publishers, 2002. (BibTeX) (More info)

2012

1. F. Ghani Zadegan, U. Ingelsson, G. Carlsson, E. Larsson:
   Reusing and retargeting on-chip instrument access procedures in IEEE P1687
   Design & Test of Computers, IEEE, Vol. PP, No. 99, pp. 1-1, 2012. (BibTeX) (More info)
2. F. G. Zadegan, U. Ingelsson, G. Carlsson, E. Larsson:
   Access Time Analysis for IEEE P1687
   I.E.E.E. transactions on computers (Print), Vol. 61, No. 10, pp. 1459-1472, 2012. (BibTeX) (More info)
3. B. SenGupta, U. Ingelsson, E. Larsson:
   Scheduling Tests for 3D Stacked Chips under Power Constraints
   Journal of Electronic Testing, Vol. 28, No. 1, pp. 121-135, 2012. (BibTeX) (More info)
4. F. G. Zadegan, U. Ingelsson, G. Carlsson, E. Larsson:
   Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
   IEEE Design & Test Magazine, Vol. 29, No. 2, pp. 79-88, 2012. (BibTeX) (More info)

2008

5. E. Larsson:
   An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
   IET Computers and digital techniques, Vol. 2, No. 4, pp. 275-284, 2008. (BibTeX) (More info)
6. E. Larsson, Z. Peng:
   A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
   Journal of electronic testing, Vol. 24, No. 5, pp. 497-504, 2008. (BibTeX) (More info)
7. S. Samii, M. Selkälä, E. Larsson, K. Chakrabarty, Z. Peng:
   Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 5, pp. 973-977, 2008. (BibTeX) (More info)

2007

8. E. Larsson, S. Edbom:
   Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint
   IET Computers and digital techniques, Vol. 1, No. 1, pp. 27-37, 2007. (BibTeX) (More info)

2006

9. E. Larsson, H. Fujiwara:
   System-on-chip test scheduling with reconfigurable core wrappers
   IEEE Transactions on Very Large Scale Integration (vlsi) Systems, Vol. 14, No. 3, pp. 305-309, 2006. (BibTeX) (More info)
10. E. Larsson, Z. Peng:
    Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
    I.E.E.E. transactions on computers (Print), Vol. 55, No. 2, pp. 227-239, 2006. (BibTeX) (More info)

2005

11. E. Larsson, J. Pouget, Z. Peng:
    Multiple Constraints Driven System-on-Chip Test Time Optimization
    Journal of electronic testing, Vol. 21, No. 6, pp. 599-611, 2005. (BibTeX) (More info)
12. E. Larsson, J. Pouget, Z. Peng:
    Abort-on-Fail Based Test Scheduling
    Journal of electronic testing, Vol. 21, No. 6, pp. 651-658, 2005. (BibTeX) (More info)

2004

13. E. Larsson:
    Preemptive system-on-chip test scheduling
    IEICE transactions on information and systems, Vol. E87D, No. 3, pp. 620-629, 2004. (BibTeX) (More info)
14. E. Larsson, K. Arvidsson, H. Fujiwara, Z. Peng:
    Efficient test solutions for core-based designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 5, pp. 758-775, 2004. (BibTeX) (More info)

2002

15. E. Larsson, Z. Peng:
    An Integrated Framework for the Design and Optimization of SOC Test Solutions
    Journal of electronic testing, Vol. 18, No. 05-apr, pp. 385-400, 2002. (BibTeX) (More info)

2012

1. E. Larsson, F. Ghani Zadegan:
   Accessing Embedded DfT Instruments with IEEE P1687
   Asian Test Symposium, Niigata, Japan, pp. 71-76, 2012-11-20. (BibTeX) (More info)
2. E. Larsson, K. Shibin:
   Fault management in an IEEE P1687 (IJTAG) environment
   2012 IEEE 15th International Symposium on Design and Diagnostics of ??? Electronic Circuits and Systems, Tallinn, Estonia, pp. 7-7, 2012-04-18. (BibTeX) (More info)
3. X. Gu, J. Rearick, B. Eklow, J. Qian, A. Jutman, K. Chakrabarty, E. Larsson:
   Re-using Chip Level DFT at Board Level
   European Test Symposium, Annecy, France, pp. 205-205, 2012-05-28. (BibTeX) (More info)
4. B. Sen Gupta, U. Ingelsson, E. Larsson:
   Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
   2012 25th International Conference on VLSI Design, Hyderbad, India, pp. 442-447, 2012-01-07. (BibTeX) (More info)
5. K. Petersen, D. Nikolov, U. Ingelsson, G. Carlsson, E. Larsson:
   An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment
   IEEE European Test Symposium (ETS), Annecy, France, 2012-05-28. (In press) (BibTeX) (More info)

2011

6. F. G. Zadegan, U. Ingelsson, G. Asani, G. Carlsson, E. Larsson:
   Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
   Test Symposium (ATS), 2011 20th Asian, New Delhi, India, pp. 525-531, 2011-11-20. (BibTeX) (More info)
7. B. SenGupta, U. Ingelsson, E. Larsson:
   Scheduling Tests for 3D Stacked Chips Under Power Constraints
   6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, 2011. (BibTeX) (More info)
8. F. G. Zadegan, U. Ingelsson, G. Carlsson, E. Larsson:
   Design Automation for IEEE P1687
   Design, Automation and Test in Europe (DATE 2011),, Grenoble, France., 2011. (BibTeX) (More info)
9. B. SenGupta, U. Ingelsson, E. Larsson:
   Scheduling Tests for 3D Stacked Chips under Power Constraints
   6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, pp. 72-77, 2011. (BibTeX) (More info)
10. D. Nikolov, U. Ingelsson, V. Singh, E. Larsson:
    Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
    5th Workshop on Dependable and Secure Nanocomputing, Hong Kong, pp. 59-64, 2011-06-27. (BibTeX) (More info)
11. P. Subramanyan, V. Singh, K. Saluja, E. Larsson:
    Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
    Computer Design (ICCD), 2011 IEEE 29th International Conference on, Amherst, MA, USA, pp. 419-426, 2011-10-09/2011-10-12. (BibTeX) (More info)
12. U. Ingelsson, S. Y. Chang, E. Larsson:
    Measurement Point Selection for In-Operation Wear-Out Monitoring
    14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany,, April 13-15 2011. (BibTeX) (More info)

2010

13. M. Majeed, D. Ahlström, U. Ingelsson, G. Carlsson, E. Larsson:
    Efficient Embedding of Deterministic Test Data
    19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010. (BibTeX) (More info)
14. F. G. Zadegan, U. Ingelsson, G. Carlsson, E. Larsson:
    Test Time Analysis for IEEE P1687
    19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010. (BibTeX) (More info)
15. E. Larsson, B. Vermeulen, K. Goossens:
    Checking Pipelined Distributed Global Properties for Post-silicon Debug
    Workshop on RTL and DFT (WRTLT10), Shanghai, China, December, 2010. (BibTeX) (More info)
16. P. Subramanyan, V. Singh, K. K. Saluja, E. Larsson:
    Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
    Design Automation and Test in Europe (DATE), Dresden, Germany, pp. 1572-1577, March 8-12, 2010. (BibTeX) (More info)
17. B. SenGupta, U. Ingelsson, E. Larsson:
    Power Constrained Test Scheduling for 3D Stacked Chips : (poster)
    1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA, 2010. (BibTeX) (More info)
18. N. S. Vinay, I. Rawat, M. S. Gaur, E. Larsson, V. Singh:
    Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
    IEEE East-West Design and Test Symposium (EWDTS10), St. Petersburg, Russia, September 17-20, 2010. (BibTeX) (More info)
19. J. T. Tudu, E. Larsson, V. Singh:
    Test Scheduling of Modular System-on-Chip under Capture Power Constraint
    Workshop on RTL and DFT (WRTLT10), Shanghai, China, December, 2010. (BibTeX) (More info)
20. D. Nikolov, U. Ingelsson, V. Singh, E. Larsson:
    Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
    5th IEEE Intl. Symposium on Electronic Design, and Applications (DELTA 2010), Ho Chi Minh City, Vietnam, pp. 281-285, January 13-15, 2010. (BibTeX) (More info)
21. P. Subramanyan, V. Singh, K. K. Saluja, E. Larsson:
    Energy-Efficient Redundant Execution for Chip Multiprocessors
    Great Lakes Symposium on VLSI (GLSVLSI'10), Rhode Island, USA,, pp. 143-146, May 16-18, 2010. (BibTeX) (More info)
22. J. T. Tudu, E. Larsson, V. Singh, H. Fujiwara:
    Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
    Great Lakes Symposium on VLSI (GLSVLSI'10), Rhode Island, USA,, pp. 73-78, May 16-18, 2010. (BibTeX) (More info)
23. J. T. Tudu, E. Larsson, V. Singh, H. Fujiwara:
    Scan Cells Reordering to Minimize Peak Power During Test Cycle :  A Graph Theoretic Approach
    IEEE European Test Symposium (ETS'10), Prague, Czech Republic, pp. 259-259, May 24-28, 2010. (BibTeX) (More info)
24. P. Subramanyan, V. Singh, K. K. Saluja, E. Larsson:
    Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
    The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10)Chicago, Illinois, USA, June 28-July 1, 2010., Fairmont Chicago, Millenium Park, pp. 121-130, 2010. (BibTeX) (More info)
25. E. Larsson, B. Vermeulen, K. Goossens:
    A Distributed Architecture to Check Global Properties for Post-Silicon Debug
    IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010. (BibTeX) (More info)

2009

26. P. Subramanyan, R. R. Jangir, J. T. Tudu, E. Larsson, V. Singh:
    Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
    7th IEEE East-West Design and Test Symposium (EWDTS), Moscow, Russia, pp. 1-4, September 18-21, 2009. (BibTeX) (More info)
27. P. Subramanyan, V. Singh, K. K. Saluja, E. Larsson:
    Power Efficient Redundant Execution for Chip Multiprocessors
    Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, pp. 1-6, June 29, 2009. (BibTeX) (More info)
28. J. T. Tudu, E. Larsson, V. Singh, V. Agrawal:
    On Minimization of Peak Power for Scan Circuit during Test
    European Test Symposium (ETS 2009), Sevilla, Spain, pp. 25-30, May 25-29, 2009. (BibTeX) (More info)
29. N. S. Vinay, E. Larsson, V. Singh:
    Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
    DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Tes, t, Nice, France, April 20-24, 2009. (BibTeX) (More info)
30. D. Adolfsson, J. Siew, E. J. Marinissen, E. Larsson:
    On Scan Chain Diagnosis for Intermittent Faults
    IEEE Asian Test Symposium (ATS), Taichung, Taiwan, pp. 47-54, November 23-26, 2009. (BibTeX) (More info)
31. J. T. Tudu, E. Larsson, V. Singh, H. Fujiwara:
    Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
    10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), Hongkong, China, pp. 43-48, November 27-28, 2009. (BibTeX) (More info)
32. V. Rajesh, E. Larsson, M. S. Gaur, V. Singh:
    An Even-Odd DFD Technique for Scan Chain Diagnosis
    Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November 27-28, 2009. (BibTeX) (More info)
33. J. T. Tudu, E. Larsson, V. Singh, A. Singh:
    Capture Power Reduction for Modular System-on-Chip Test
    IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 8-10, 2009. (BibTeX) (More info)
34. M. Vayrynen, V. Singh, E. Larsson:
    Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
    Design Automation and Test in Europe (DATE 2009), Nice, France, pp. 484-489, April 20-24, 2009. (BibTeX) (More info)

2008

35. M. Söderman, E. Larsson:
    Test Response Compression for Diagnosis in Volume Production
    DAC08 Workshop on Diagnostic Services in Network-on-Chips DSNOC, 2008. (BibTeX) (More info)
36. A. Larsson, X. Zhang, E. Larsson, K. Chakrabarty:
    Core-Level Expansion of Compressed Test Patterns
    17th Asian Test Symposium ATS, pp. 277-, 2008. (BibTeX) (More info)
37. V. Singh, E. Larsson:
    On Reduction of Capture Power for Modular System-on-Chip Test
    IEEE Workshop on RTL and High Level Testing WRTLT08, 2008. (BibTeX) (More info)
38. A. Larsson, E. Larsson, K. Chakrabarty, P. I. Eles, Z. Peng:
    Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
    Design, Automation, and Test in Europe DATE 2008, pp. 188-, 2008. (BibTeX) (More info)

2007

39. T. Dubois, E. J. Marinissen, M. Azimane, P. Wielage, E. Larsson, C. Wouters:
    Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
    Design, Automation, and Test in Europe DATE, pp. 859-, 2007. (BibTeX) (More info)
40. G. Carlsson, J. Holmqvist, E. Larsson:
    Protocol Requirements in an SJTAG/IJTAG Environment
    International Test Conference, pp. 1.3-, 2007. (BibTeX) (More info)
41. A. Larsson, E. Larsson, P. I. Eles, Z. Peng:
    A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
    IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 61-, 2007. (BibTeX) (More info)
42. E. Larsson, M. Amirijoo, D. Karlsson, P. I. Eles:
    What Impacts Course Evaluation?
    12th SIGCSE Conf. on Innovation and Technology in Computer Science Education, pp. 333-333, 2007. (BibTeX) (More info)
43. J. Holmqvist, G. Carlsson, E. Larsson:
    Extended STAPL as SJTAG Engine
    IEEE European Test Symposium, pp. 119-, 2007. (BibTeX) (More info)
44. E. Larsson, J. Persson:
    An Architecture for Combined Test Data Compression and Abort-on-Fail Test
    Asia and South Pacific Design Automation Conference, pp. 726-, 2007. (BibTeX) (More info)
45. A. Larsson, E. Larsson, P. I. Eles, Z. Peng:
    Optimized Integration of Test Compression and Sharing for SOC Testing
    Design, Automation, and Test in Europe Conference DATE07, pp. 207-, 2007. (BibTeX) (More info)

2006

46. E. Larsson:
    Combined Test Data Compression and Abort-on-Fail Test
    24th IEEE Norchip Conference, 2006. (BibTeX) (More info)
47. S. Samii, E. Larsson, K. Chakrabarty, Z. Peng:
    Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
    International Test Conference, pp. 32.1-, 2006. (BibTeX) (More info)

2005

48. U. Ingelsson, S. K. Goel, E. Larsson, E. J. Marinissen:
    Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
    IEEE European Test Symposium ETS 05, 2005. (BibTeX) (More info)
49. A. Larsson, E. Larsson, P. I. Eles, Z. Peng:
    Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
    8th Euromicro Conference on Digital System Design DSD2005, pp. 403-, 2005. (BibTeX) (More info)
50. E. Larsson, I. Gilani:
    A Test Data Compression Architecture with Abort-on Fail Capability
    IEEE Workshop on RTL and High Level Testing WRTLT, 2005. (BibTeX) (More info)
51. E. Larsson, S. Edbom:
    Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
    IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005}, pp. 429-434, 2005. (BibTeX) (More info)
52. A. Larsson, E. Larsson, P. I. Eles, Z. Peng:
    SOC Test Scheduling with Test Set Sharing and Broadcasting
    IEEE Asian Test Symposium, pp. 162-, 2005. (BibTeX) (More info)
53. D. Bäckström, G. Carlsson, E. Larsson:
    Remote Boundary-Scan System Test Control for the ATCA Standard
    International Test Conference ITC05, pp. 32.2-, 2005. (BibTeX) (More info)

2004

54. E. Larsson, A. Larsson:
    Student-oriented Examination in a Computer Architecture Course
    9th Annual Conference on Innovation and Technology in Computer Science Education, pp. 245-245, 2004. (BibTeX) (More info)
55. S. Edbom, E. Larsson:
    An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
    2004 IEEE Asian Test Symposium ATS 2004, pp. 254-, 2004. (BibTeX) (More info)
56. E. Larsson, J. Pouget, Z. Peng:
    Defect-Aware SOC Test Scheduling
    2004 IEEE VLSI Test Symposium VTS04, pp. 359-, 2004. (BibTeX) (More info)
57. E. Larsson:
    Integrating Core Selection in the SOC Test Solution Design-Flow
    International Test conference ITC04, pp. 1349-, 2004. (BibTeX) (More info)
58. A. Larsson, E. Larsson, P. I. Eles, Z. Peng:
    A Technique for Optimization of System-on-Chip Test Data Transportation
    9th IEEE European Test Symposium, pp. 179-180, 2004. (BibTeX) (More info)

2003

59. J. Pouget, E. Larsson, Z. Peng, M. L. Flottes, B. Rouzeyre:
    An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
    IEEE European Test Workshop 2003 ETW03, pp. 51-, 2003. (BibTeX) (More info)
60. E. Larsson, J. Pouget, Z. Peng:
    Defect Probability-based System-On-Chip Test Scheduling
    6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS03,2003, pp. 25-32, 2003. (BibTeX) (More info)
61. J. Pouget, E. Larsson, Z. Peng:
    SOC Test Time Minimization Under Multiple Constraints
    12th IEEE Asian Test Symposium ATS03, pp. 312-, 2003. (BibTeX) (More info)
62. E. Larsson, H. Fujiwara:
    Test Resource Partitioning and Optimization for SOC Designs
    2003 IEEE VLSI Test Symposium VTS03, pp. 319-, 2003. (BibTeX) (More info)
63. E. Larsson, Z. Peng:
    A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
    International Test Conference ITC 2003, pp. 1135-, 2003. (BibTeX) (More info)
64. E. Larsson, H. Fujiwara:
    Optimal System-on-Chip Test Scheduling
    12th IEEE Asian Test Symposium ATS03, pp. 306-, 2003. (BibTeX) (More info)
65. A. Larsson, E. Larsson, P. I. Eles, Z. Peng:
    Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
    18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03, pp. 385-, 2003. (BibTeX) (More info)

2002

66. E. Larsson, K. Arvidsson, H. Fujiwara, Z. Peng:
    Integrated Test Scheduling, Test Parallelization and TAM Design
    IEEE Asian Test Symposium ATS02, pp. 397-, 2002. (BibTeX) (More info)
67. E. Larsson, H. Fujiwara:
    Power Constrained Preemptive TAM Scheduling
    7th IEEE European Test Workshop,2002, pp. 119-, 2002. (BibTeX) (More info)

2001 and earlier

68. E. Larsson, Z. Peng:
    An Integrated System-On-Chip Test Framework
    Design, Automation and Test in Europe DATE Conference, pp. 138-, 2001. (BibTeX) (More info)
69. E. Larsson, Z. Peng, G. Carlsson:
    The Design and Optimization of SOC Test Solutions
    ICCAD-2001, pp. 523-, 2001. (BibTeX) (More info)
70. E. Larsson, Z. Peng:
    Test Scheduling and Scan-Chain Division Under Power Constraint
    Tenth Asian Test Symposium ATS 2001, pp. 259-, 2001. (BibTeX) (More info)
71. E. Larsson, Z. Peng:
    System-on-Chip Test Bus Design and Test Scheduling
    International Test Synthesis Workshop,2000, 2000. (BibTeX) (More info)
72. E. Larsson, Z. Peng:
    A Technique for Test Infrastructure Design and Test Scheduling
    Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS, pp. 26-, 2000. (BibTeX) (More info)