International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR), 2009-2012
International Workshop on Reliability Aware System Design and Test (RASDAT), 2010-2013
Asia Pacific Conference on Circuits and Systems (APCCAS), 2010
International Workshop on Network on Chip Architectures (NoCArc), 2010
5th Workshop on Dependable and Secure Nanocomputing (WDSN), 2011
Invited talks, keynotes, tutorials
Erik Larsson and Konstantin Shibin, Fault management in an IEEE P1687 (IJTAG) environment (Tutorial), IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Tallinn, Estonia, April 2012 (PDF).
Gunnar Carlsson, Artur Jutman and Erik Larsson, SoC-Level Fault Management based on P1687 IJTAG (Tutorial), DIAMOND tutorial at DATE'11: Handling the challenges of debugging and reliability, Grenoble, France, March 2011.
Erik Larsson, Testing advanced electronics systems (Tutorial), IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Malaysia, December 2010.
Erik Larsson, A Distributed Architecture for Checking Global Properties during Post Silicon Debug (Elevator talk), International Test Conference (ITC), Austin, Texas, USA, November 2010.
Erik Larsson, Checking distributed properties during post silicon debug (Invited talk), Tallinn Technical University, Tallinn, Estonia, February 2010.
Erik Larsson, Throughput and Diagnosis - Co-Maximization (Elevator talk), International Test Conference (ITC), Austin, Texas, USA, November 2009.
Erik Larsson, Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chip (Invited talk), Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium, May 2009.
Erik Larsson, Power-Aware SOC Test Planning (Keynote), Workshop on RTL and High Level Testing (WRTLT), Sapporo, Japan, November 2008.
Erik Larsson, Improved Scan-Chain Diagnosis (Invited talk), SAAB, Linköping, Sweden, May 2008.
Erik Larsson, An X-Tolerant and Diagnostic Friendly Approach to Integrate Abort-on-Fail Test and Test Data Compression in a Multi-site Environment (Invited talk), University of Bologna, Bologna, Italy, May 2008.
Erik Larsson, Power-Constrained Test Design for Modular System-on-Chip (Invited talk), Indian Institute of Science, Bangalore, India, January 2008.
Erik Larsson, An X-Tolerant and Diagnostic Friendly Approach to Integrate Abort-on-Fail Test and Test Data Compression in a Multi-site Environment (Invited talk), Synopsis, San Jose, CA, USA, October 2007.
Erik Larsson, Testing System Chips (Invited talk), NXP Semiconductors - Corporate Innovation & Technology, Eindhoven, The Netherlands, September 2007.
Erik Larsson, Testing System Chips (Invited talk), Indian Institute of Science, Bangalore, India, August 2007.
Erik Larsson and Krishnendu Chakrabarty (Tutorial), Manufacturing Test Solutions for System-On-Chip Integrated Circuits, VLSI Design and Test Symposium (VDAT), Kolkata, India, August 2007.
Erik Larsson, Testing System Chips (Invited talk), The Chinese University of Hong Kong, Hong Kong, China, January 2007.
Erik Larsson, Testing System Chips (Invited talk), Nara Institute of Science and Technology, Nara, Japan, January 2007.
Erik Larsson, Test Preparation and Application for System Chips (Invited talk), Tallinn Technical University, Tallinn, Estonia, September 2006.
Erik Larsson, Test Preparation and Application for System Chips (Invited talk), Universität Potsdam, Potsdam, Germany, May 2006.
Erik Larsson, Design and Optimization of System-on-Chip Test Solutions (Invited talk), Philips Research, Eindhoven, The Nederlands, October 2003.
Erik Larsson, Integrated Test Scheduling and Test Access Mechanism Design for System-on-Chip Designs (Invited talk), Hitachi Central Research Laboratory, Tokyo, Japan, October 2002.
