VINNOVA Industrial Excellence Center - System Design on Silicon
2008-01-01 -> 2017-12-31
Wireless communication devices, such as a mobile phone, is quickly changing from a single-network voice communication device with rudimentary messaging capabilities to a portable multi-network hub with extensive multi-media capabilities. This scenario sets several challenges that have to be addressed. The proposed center will mainly focus on one of them, the system design on silicon.
Rapid development and technology evolution have changed the marketplace substantially in the last decade. These changes include:
- Multi-standard: Mobile terminal evolution from a device incorporating a single standard to a multi-standard device, as illustrated in Fig 1. Today we see an even greater challenge, which is to achieve concurrent and efficient reception and transmission of multiple data streams, e.g. GSM, WLAN and GPS.
- Multi-media: Increasingly advanced multi-media processing is performed within the terminal. This is increasing at an incredible rate to facilitate recording, displaying and wireless transmission of many different types of digital media.
- Power consumption: Battery lifetime will not be allowed to decrease when more and more functionality is incorporated into the mobile hub. Further, battery development is considerably slower than the increase in processing requirements. As a consequence very high demands will be put on the evolution of low-power electronics.
We attack these issues by taking advantage of the vast opportunities that system design on silicon gives us. The interoperability of applications and networks will certainly lead to new services, changing user behavior, in turn leading to higher user requirements and expanding business opportunities. For manufacturers of mobile terminals this interoperability is a major challenge, since the terminals need to become increasingly complex and flexible to sustain emerging standards and applications, while at the same time maintaining the battery lifetime. In addition, the increasing need for functional flexibility in radio systems combined with the huge costs of System-on-Chip (SoC) design will make implementation of wireless standards and multi-media applications on silicon platforms a true scientific challenge in the coming years. The scenario we have presented poses some specific hardware challenges which have to be addressed. These include:
- Increased system complexity due
- more standards in one terminal/device
- more complex radio standards
- concurrently running radio standards
- more frequency bands
- more complex multi-media schemes
- Increased platform flexibility to cope with
- the complexity of the above
- the need for platform reuse to reduce development cost
- the need to reduce silicon cost
- Increased energy efficiency
- New technology nodes which during the lifetime of the center will change how we design circuits.
The above will affect all areas of hardware platform design for wireless terminal devices, i.e. the radio front ends including antennas and antenna interfaces, mixed mode processing, and digital baseband as well as digital multimedia processing. However, to make an overall efficient solution the hardware has to work in harmony with the algorithms and cannot stand as a separate entity. Therefore, the proposed center will attack the above research challenges both from a circuit and a system perspective, emphasizing novel solutions that will advance state of the art. The center will combine the knowledge of a number of research groups and industrial partners in an efficient and well balanced interdisciplinary effort. We want to utilize the broad knowledge base available among the partners and exploit the synergy effects obtained by exercising more than one domain. The strength of the constellation is its combination of system and algorithm research being performed in close cooperation with hardware implementation. Furthermore, the center will work in close cooperation with Swedish and international industry. The proposed research will lead to ideas and solutions that open up many possibilities for Swedish industry beyond 3G systems. Those are the guiding principles under which we propose this Industrial Excellence Center in the area of system design on silicon, providing a multi-faceted and holistic approach to the design of platforms for future wireless terminals.
Trends and Challenges
Current trends and challenges within the area of system design on silicon was briefly outlined in the introduction, with a special perspective regarding wireless communication devices. In this section we specify these in more detail while at the same time sketching scenarios that will become important during the 10 year span of the center. Following this, a research program is outlined in the next section with a more focused approach.
Challenge 1. Multiple Radio Access Standards
During the last decade we have seen that the number of standards within a mobile phone has increased from a single one with a few flavors to an ever increasing set that is much more diversified. Of course it is possible to develop solutions by just combining circuitry designed for the individual standards, but this leads to a high silicon cost. Therefore, a large research effort has been dedicated to find solutions that allow a more flexible hardware platform incorporating several standards on the same piece of silicon. The ultimate solution is a single programmable transceiver handling all existing and upcoming standards for mobile communications.
At the same time both the number of standards as well as the number of frequency bands has increased, and will continue to do so. This increases the complexity and cost of mobile phones, e.g. in today’s solutions several filters are needed for each frequency band. Due to the increased number of frequency bands, the number of antenna elements also grows quickly, which is hard to combine with a small physical size of the mobile device. Adaptive antenna interfaces that reduce the number of antenna elements and filters are therefore necessary. This is not to oppose concepts in the area of multiple antenna systems which we are sure will mature during the lifetime of the proposed center. Within the realm of modulation and coding, different schemes are required for the various standards and the signal-to-noise ratios that may occur. The multimedia scenario requires that a number of source coding schemes coexist. Power conservation algorithms and system designs are of course crucial. All of these must coexist harmoniously and as much as possible use the same processing and memory resources.
Challenge 2. Concurrent Connectivity
Taking the mobile terminal one step further, we envision that those multiple radio standards should not just run on the same platform, but they should also run simultaneously. This setup, of course, poses new problems with respect to the complexity of the platform. Multiple signals at different carrier frequencies have to be treated simultaneously on the radio frequency/antenna side as well as in an aggregated baseband signal in the digital domain. On top of these, we will require several data compression, multimedia processing and error control algorithms running at the same time, on the same platform, without wasting resources.
Challenge 3. Platforms for Wireless Communication
In challenges 1 and 2 we have seen that from the system perspective the complexity will grow at an ever increasing rate calling for flexible platforms. At the same time the silicon cost should not increase and the platform should be both adaptable over several generations and flexible to a wide variety of scenarios. Unfortunately there is a contradiction between flexibility and energy efficiency and this trade-off is not an easy task. Large advancements have been made within this field, which is often labeled Software Defined Radio (SDR) or Flexible Radios. However, this task is far from solved and there are still vast research opportunities.
Challenges regarding wireless platforms arise within all individual fields within circuit and embedded system design, i.e. RF, mixed mode and digital baseband design. In RF one of the main challenges is the antenna interface. To achieve flexibility the fixed frequency RF filters and duplexers must be eliminated. This puts stringent requirements on transmitter noise emissions and receiver linearity. It also requires new concepts like active duplexers to be introduced. Another major challenge is the simultaneous use of two different systems in the same device, especially if the fixed frequency RF filters are removed. Severe disturbances between transmitting and receiving systems are to be expected. Even when in pure receive mode the different frequency synthesizers used simultaneously on the same chip will disturb each other.
Within mixed mode design, a number of challenges arise from the need for filtering and converting two or more signals from the analog to the digital domain. At least partially, this new situation can be addressed with a brute-force approach, i.e. by duplicating the number of blocks performing the named operations. This is acceptable, as the never-ending CMOS scaling allows for increased levels of functionality for a constant silicon area. This is not to say that we should not look for more innovative approaches, such as an early digitization of all concurrent signals in one and the same analog-to-digital converter. This lifts much of the complexity from the analog to the digital domain, where we can harvest the full power of state-of-the-art nanometer CMOS processes. In this sense, two digital-friendly converter architectures should be investigated: the capacitive successive-approximation topology, and the time-continuous sigma-delta (oversampling) topology. The former is remarkable in that it basically does not make use of MOS devices as transistors, but rather as switches, in much the same fashion as a truly digital block; the latter can take advantage of the increased clock frequency (for a constant power consumption) to achieve a higher selectivity and/or conversion bandwidth.
Regarding digital baseband processing there are two main considerations: First, the increased complexity of processing due to higher cellular bit rates, more complex algorithms, multiple standards and the concurrency, will require aggregated data handling capabilities; second, coping with energy efficient processing under the flexibility considerations due to challenges 1 and 2. A dedicated solution has a cost advantage for large volume applications, basically consumer electronics, while other applications need a dedicated solution from a power or performance perspective, which thus are prepared to accept an increased cost. However, the power density in integrated circuits has become a severe constraint that requires new solutions both on the circuit and the architectural level. On an architectural level new solutions need to solve both computational bottlenecks and severe energy constraints.
Challenge 4. Platforms for Multi Media Processing
Seeing the mobile phone being transformed to a multimedia hub means that a large part of the resources within a phone is dedicated to processing of multimedia signals where images and image generation (i.e. three-dimensional graphics) are the most demanding ones. Over the past years, it has become clear that three-dimensional graphics and other types of multimedia, such as video, TV, animated messages, etc are more and more important for a mobile device. The major reason is that the visual content (and its quality) is a major differentiating factor, and if that is well done the device is likely to be more successful. A distinct example of this is the Apple iPhone, which appears to be a huge success worldwide. Standards and features in this field also change at a fast pace and also here flexible platforms are required. To be able to achieve these tasks at reasonable energy consumption with high image quality, dedicated hardware platforms are required.
Challenge 5. Energy Efficiency
Power consumption, or more specifically energy consumption, is a crucial parameter for all devices being battery operated. Incorporating challenges 1-4 above will increase the energy consumption manifold if nothing is done to challenge it. Of course the last decades have shown great advances in low power circuit design both in reducing the active power and the stand-by one. At the same time battery efficiency has only improved approximately 10 times in the last 100 years and our belief is that solutions to extended battery life with increased complexity terminals are to be found in the design of the electronics. Dedicated hardware solutions are the most energy efficient ones but unfortunately this contradicts the demand for flexible and programmable solutions. Therefore, low energy consumption has to be a guiding factor for all decisions ranging from system and algorithmic design down to the silicon realization. Furthermore, the power profile of the digital circuits, making up a large part of the terminal, is becoming even worse. Traditionally leakage power was ignored and only the dynamic power consumption was considered. However, with shrinking feature sizes of the CMOS devices the static, or leakage, power takes an ever increasing part and is believed to become a sizable (even major) fraction of the total power budget depnding on the application.
Another major energy consumer in the terminal is the transmitters. At peak output power a mobile phone transmitter consumes several Watts. Improved transmitter efficiency is therefore critical in extending the battery life. The efficiency must be improved at the same time as other requirements such as flexibility, linearity, and noise emissions are met. These requirements will be significantly increased due to challenges 1-3 above, making the transmitter one of the most difficult parts to solve.
Challenge 6. Evolving Technologies
Scaling of the Si-transistor technology has been the driving force for increasing speed and transistor density over the last decades. However, scaling gets more difficult as we continue to scale down beyond the 65 nm node and we face problems related to gate leakage through the thin gate oxide and poor potential control in the channel. Even though scaling has reduced the power consumption per transistor, the increase in density has resulted in an increase in the energy dissipation per unit area of the chip. Current trends on the device level include the introduction of high-K materials as gate dielectric to reduce leakage, the use of novel transistor architectures (FinFETs, Tri-gates or Wrap-gates) for improved potential control, and even the introduction of alternative channel materials (Ge, SiGe, III/Vs) to achieve “More than Moore”. Several manufacturers are pursuing different approaches and substantial improvement on the transistor performance has been achieved. It is critical to follow the development in order to access the best technology possible.For RF and mixed signal design, especially the power amplifier and antenna interface parts, the choice of technology must be carefully considered. As the supply voltage of current and future standard CMOS technology seems to be limited to about 1V, other technologies must be investigated. One alternative is LDMOS, which would allow the supply voltages needed by transmitters by adding a few process steps to standard CMOS. Also CMOS on Sapphire and other SoI processes are interesting.