Designing NoC slot allocation algorithms in HW/SW
Andreas Hansson (D00)
Systems on chip (SoC) show a growing trend when it comes to the amount of modules on chip as well as their complexity and clock frequency. This has created a need for modularization and decoupling of building blocks leading to a diversity of modules with high demands on connectivity. Traditionally this communication has been done over a shared bus, where devices arbitrate for exclusive access to the shared medium. Networks on chip (NoC) pose an attractive alternative. Herein peers communicate via a network that allows for sharing of wires, and higher wire utilization, using packet-based communication in a time multiplexed fashion. The network also structures wires and helps in overcoming electrical problems arising with deep-submicron technologies.
On-chip networks share many aspects with traditional off-chip networks but differ in some crucial regards. Firstly, the constraints limit the design space and necessitate a reevaluation of design choices. Secondly, the well-known architecture of the network allows for a tighter synchronization between nodes. A cost-effective way of providing throughput and latency guarantees in such a network is to use time-division multiple access (TDMA) pipelined circuits, where each connection is reserved time slots forming a virtual circuit. Best effort traffic can then use the left over time slots, thereby increasing utilization.
Allocating slots to multiple connections with timing demands constitute a highly computational intensive problem. Even more dimensions are added to the problem when considering multiple task graphs (changing over time) and a freedom in choosing connection paths to avoid hot spots. With a processor connected to the network, the configuration can be done through the network itself. By looping a port on the network interfaces (NI), bridging between intellectual property blocks (IP) and the router network, to a memory mapped configuration port on the same NI, configuration register files can be accessed though normal read and write operations sent as packets over the network.
On such a processor a time slot allocation algorithm should be designed, implemented, and evaluated. The possibility of using hardware acceleration for increased efficiency shall be explored together with a diversity of algorithmic choices. Being able to do the above implies solving the following problems:
- Constructing a functioning configuration interface for the NI
- Introducing an ARM processor in the NoC simulator
- Designing algorithms for configuration, which can offer network guarantees
- Optimize said algorithms for high performance
- Investigating the advantages of hardware acceleration in slot allocation
Advisor: Kees Goosens (ESAS, Philips Research) and Lambert Spaanenburg (EIT)