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Referens:
Title:
Design of coarse-grained dynamically reconfigurable architecture for DSP applications
International Conference on Reconfigurable Computing and FPGAs
Type:
conference paper
Keywords:
Coarse-grained reconfigurable architecture, FFT., Dynamically reconfigurable cell array, Hybrid interconnect
Abstract:
This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.
Year:
2009
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